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89 lines
2.8 KiB
LLVM
89 lines
2.8 KiB
LLVM
; RUN: llc -march=hexagon -disable-hexagon-peephole < %s | FileCheck %s
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; Test that we're generating a 32-bit multiply high instead of a 64-bit version,
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; when using the high 32-bits only.
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; CHECK-LABEL: f0:
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; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = mpy(
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define void @f0(i32* nocapture readonly %a0, i32* nocapture %a1) #0 {
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b0:
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%v0 = getelementptr i32, i32* %a1, i32 448
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br label %b1
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b1: ; preds = %b1, %b0
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b1
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%v1 = getelementptr inbounds i32, i32* %a0, i32 64
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%v2 = load i32, i32* %a0, align 4
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%v3 = getelementptr inbounds i32, i32* %a0, i32 2
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%v4 = load i32, i32* %v1, align 4
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%v5 = sext i32 %v2 to i64
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%v6 = sext i32 %v4 to i64
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%v7 = mul nsw i64 %v6, %v5
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%v8 = lshr i64 %v7, 32
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%v9 = trunc i64 %v8 to i32
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%v10 = sub nsw i32 0, %v9
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%v11 = getelementptr inbounds i32, i32* %v0, i32 1
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store i32 %v10, i32* %v1, align 4
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ret void
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}
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; Similar to above, but using the operands of the multiply are expressions.
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; CHECK-LABEL: f1:
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; CHECK: r{{[0-9]+}} = mpy(
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define void @f1(i32 %a0, i32 %a1, i32* nocapture readonly %a2, i32* nocapture %a3) #0 {
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b0:
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%v0 = getelementptr i32, i32* %a3, i32 448
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br label %b1
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b1: ; preds = %b1, %b0
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b1
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%v1 = getelementptr inbounds i32, i32* %a2, i32 64
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%v2 = sext i32 %a0 to i64
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%v3 = sext i32 %a1 to i64
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%v4 = mul nsw i64 %v3, %v2
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%v5 = lshr i64 %v4, 32
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%v6 = trunc i64 %v5 to i32
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%v7 = sub nsw i32 0, %v6
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%v8 = getelementptr inbounds i32, i32* %v0, i32 1
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store i32 %v7, i32* %v1, align 4
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ret void
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}
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; Check that the transform occurs when the loads can be post-incremented.
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; CHECK-LABEL: f2:
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; CHECK: r{{[0-9]+}} = mpy(
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define void @f2(i32* nocapture readonly %a0, i32* nocapture %a1) #0 {
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b0:
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%v0 = getelementptr i32, i32* %a1, i32 448
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br label %b1
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b1: ; preds = %b0
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%v1 = getelementptr inbounds i32, i32* %a0, i32 64
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br label %b2
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b2: ; preds = %b2, %b1
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%v2 = phi i32* [ %v0, %b1 ], [ %v14, %b2 ]
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%v3 = phi i32* [ %v1, %b1 ], [ undef, %b2 ]
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%v4 = phi i32* [ null, %b1 ], [ %v6, %b2 ]
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%v5 = load i32, i32* %v4, align 4
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%v6 = getelementptr inbounds i32, i32* %v4, i32 2
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%v7 = load i32, i32* %v3, align 4
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%v8 = sext i32 %v5 to i64
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%v9 = sext i32 %v7 to i64
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%v10 = mul nsw i64 %v9, %v8
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%v11 = lshr i64 %v10, 32
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%v12 = trunc i64 %v11 to i32
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%v13 = sub nsw i32 0, %v12
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%v14 = getelementptr inbounds i32, i32* %v2, i32 1
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store i32 %v13, i32* %v2, align 4
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br label %b2
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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