1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
llvm-mirror/test/CodeGen
Matt Arsenault 7f117abc99 R600/SI: Fix f64 inline immediates
llvm-svn: 224458
2014-12-17 21:04:08 +00:00
..
AArch64 IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
ARM [ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes 2014-12-16 10:59:27 +00:00
CPP
Generic IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Hexagon IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Inputs IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Mips [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks. 2014-12-17 10:56:16 +00:00
MSP430
NVPTX [NVPTX] Fix bugs related to isSingleValueType 2014-12-17 17:59:04 +00:00
PowerPC [PowerPC] Improve instruction selection bit-permuting operations (32-bit) 2014-12-16 05:51:41 +00:00
R600 R600/SI: Fix f64 inline immediates 2014-12-17 21:04:08 +00:00
SPARC IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
SystemZ IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb2 IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
X86 Fix CR/LF line endings in test case 2014-12-17 17:52:12 +00:00
XCore IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00