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bbd04b8c49
Summary: If a PHI has an incoming undef, we can pretend that it is equal to one non-undef, non-self incoming value. This is particularly relevant in combination with the StructurizeCFG pass, which introduces PHI nodes with undefs. Previously, this lead to branch conditions that were uniform before StructurizeCFG to become non-uniform afterwards, which confused the SIAnnotateControlFlow pass. This fixes a crash when Mesa radeonsi compiles a shader from dEQP-GLES3.functional.shaders.switch.switch_in_for_loop_dynamic_vertex Reviewers: arsenm, tstellarAMD, jingyue Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19013 llvm-svn: 266347
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn-- < %s | FileCheck %s
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; The branch instruction in LOOP49 has a uniform condition, but PHI instructions
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; introduced by the structurizecfg pass previously caused a false divergence
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; which ended up in an assertion (or incorrect code) because
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; SIAnnotateControlFlow and structurizecfg had different ideas about which
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; branches are uniform.
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;
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; CHECK-LABEL: {{^}}main:
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; CHECK: ; %LOOP49
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; CHECK: v_cmp_ne_i32_e32 vcc,
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; CHECK: s_cbranch_vccnz
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; CHECK: ; %ENDIF53
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define amdgpu_vs float @main(i32 %in) {
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main_body:
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%cmp = mul i32 %in, 2
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br label %LOOP
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LOOP: ; preds = %ENDLOOP48, %main_body
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%counter = phi i32 [ 0, %main_body ], [ %counter.next, %ENDLOOP48 ]
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%v.LOOP = phi i32 [ 0, %main_body ], [ %v.ENDLOOP48, %ENDLOOP48 ]
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%tmp7 = icmp slt i32 %cmp, %counter
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br i1 %tmp7, label %IF, label %LOOP49
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IF: ; preds = %LOOP
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%r = bitcast i32 %v.LOOP to float
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ret float %r
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LOOP49: ; preds = %LOOP
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%tmp8 = icmp ne i32 %counter, 0
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br i1 %tmp8, label %ENDLOOP48, label %ENDIF53
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ENDLOOP48: ; preds = %ENDIF53, %LOOP49
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%v.ENDLOOP48 = phi i32 [ %v.LOOP, %LOOP49 ], [ %v.ENDIF53, %ENDIF53 ]
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%counter.next = add i32 %counter, 1
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br label %LOOP
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ENDIF53: ; preds = %LOOP49
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%v.ENDIF53 = add i32 %v.LOOP, %counter
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br label %ENDLOOP48
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}
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