Reid Kleckner e262abe247 [X86] Fix register parsing in .seh_* in Intel syntax ... Previously, the parser checked for a '%' prefix to indicate a register. In Intel syntax mode, LLVM does not print a '%' prefix on registers, so LLVM could not parse its own assembly output. Instead, require that register numbers be integer literals, or at least start with an integer literal, which is consistent with .cfi_* directive register parsing. llvm-svn: 375287		2019-10-18 21:01:41 +00:00
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AArch64	[AArch64] Adding support for PMMIR_EL1 register	2019-10-18 12:40:29 +00:00
AMDGPU	[AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32	2019-10-18 14:49:53 +00:00
ARM	[lit] Fix internal diff's --strip-trailing-cr and use it	2019-10-16 17:21:57 +00:00
AsmParser	[X86] Fix register parsing in .seh_* in Intel syntax	2019-10-18 21:01:41 +00:00
AVR
BPF
COFF
Disassembler	[AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32	2019-10-18 14:49:53 +00:00
ELF	Added support for "#pragma clang section relro=<name>"	2019-10-15 18:31:10 +00:00
Hexagon
Lanai
MachO
Mips	[mips] Fix loadImmediate calls when load non-address values.	2019-10-12 07:42:44 +00:00
MSP430
PowerPC
RISCV
Sparc
SystemZ
WebAssembly	[WebAssembly] Allow multivalue signatures in object files	2019-10-18 20:27:30 +00:00
X86	[X86] Teach X86MCodeEmitter to properly encode zmm16-zmm31 as index register to vgatherpf/vscatterpf.	2019-10-14 23:48:24 +00:00