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7fce27389c
TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910
921 lines
22 KiB
YAML
921 lines
22 KiB
YAML
# RUN: llc -mtriple arm-- -global-isel -run-pass=regbankselect %s -o - | FileCheck %s
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--- |
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define void @test_add_s32() { ret void }
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define void @test_sub_s32() { ret void }
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define void @test_mul_s32() { ret void }
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define void @test_sdiv_s32() #1 { ret void }
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define void @test_udiv_s32() #1 { ret void }
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define void @test_and_s32() { ret void}
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define void @test_or_s32() { ret void}
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define void @test_xor_s32() { ret void}
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define void @test_lshr_s32() { ret void }
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define void @test_ashr_s32() { ret void }
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define void @test_shl_s32() { ret void }
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define void @test_loads() #0 { ret void }
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define void @test_stores() #0 { ret void }
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define void @test_stack() { ret void }
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define void @test_gep() { ret void }
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define void @test_constants() { ret void }
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@a_global = global float 1.0
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define void @test_globals() { ret void }
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define void @test_anyext_s8_32() { ret void }
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define void @test_anyext_s16_32() { ret void }
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define void @test_trunc_s32_16() { ret void }
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define void @test_icmp_eq_s32() { ret void }
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define void @test_fcmp_one_s32() #0 { ret void }
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define void @test_fcmp_ugt_s64() #0 { ret void }
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define void @test_select_s32() { ret void }
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define void @test_br() { ret void }
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define void @test_fadd_s32() #0 { ret void }
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define void @test_fadd_s64() #0 { ret void }
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define void @test_fsub_s32() #0 { ret void }
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define void @test_fsub_s64() #0 { ret void }
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define void @test_fmul_s32() #0 { ret void }
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define void @test_fmul_s64() #0 { ret void }
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define void @test_soft_fp_s64() #0 { ret void }
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attributes #0 = { "target-features"="+vfp2"}
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attributes #1 = { "target-features"="+hwdiv-arm" }
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...
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---
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name: test_add_s32
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# CHECK-LABEL: name: test_add_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_ADD %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sub_s32
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# CHECK-LABEL: name: test_sub_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_SUB %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_mul_s32
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# CHECK-LABEL: name: test_mul_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_MUL %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sdiv_s32
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# CHECK-LABEL: name: test_sdiv_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_SDIV %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_s32
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# CHECK-LABEL: name: test_udiv_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_UDIV %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_and_s32
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# CHECK-LABEL: name: test_and_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_AND %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_or_s32
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# CHECK-LABEL: name: test_or_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_OR %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_xor_s32
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# CHECK-LABEL: name: test_xor_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_XOR %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_lshr_s32
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# CHECK-LABEL: name: test_lshr_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_LSHR %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_ashr_s32
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# CHECK-LABEL: name: test_ashr_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_ASHR %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_shl_s32
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# CHECK-LABEL: name: test_shl_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = G_SHL %0, %1
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_loads
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# CHECK-LABEL: name: test_loads
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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# CHECK: - { id: 3, class: gprb, preferred-register: '' }
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# CHECK: - { id: 4, class: gprb, preferred-register: '' }
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# CHECK: - { id: 5, class: gprb, preferred-register: '' }
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# CHECK: - { id: 6, class: fprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0:
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liveins: %r0
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%0(p0) = COPY %r0
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%6(s64) = G_LOAD %0 :: (load 8)
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%1(s32) = G_LOAD %0 :: (load 4)
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%2(s16) = G_LOAD %0 :: (load 2)
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%3(s8) = G_LOAD %0 :: (load 1)
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%4(s1) = G_LOAD %0 :: (load 1)
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%5(p0) = G_LOAD %0 :: (load 4)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_stores
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# CHECK-LABEL: name: test_stores
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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# CHECK: - { id: 3, class: gprb, preferred-register: '' }
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# CHECK: - { id: 4, class: gprb, preferred-register: '' }
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# CHECK: - { id: 5, class: gprb, preferred-register: '' }
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# CHECK: - { id: 6, class: fprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r5, %d6
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%0(p0) = COPY %r0
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%1(s32) = COPY %r1
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G_STORE %1(s32), %0 :: (store 4)
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%2(s16) = G_TRUNC %1(s32)
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G_STORE %2(s16), %0 :: (store 2)
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%3(s8) = G_TRUNC %1(s32)
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G_STORE %3(s8), %0 :: (store 1)
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%4(s1) = G_TRUNC %1(s32)
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G_STORE %4(s1), %0 :: (store 1)
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%5(p0) = COPY %r5
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G_STORE %5(p0), %0 :: (store 4)
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%6(s64) = COPY %d6
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G_STORE %6(s64), %0 :: (store 8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_stack
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# CHECK-LABEL: name: test_stack
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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# CHECK: - { id: 3, class: gprb, preferred-register: '' }
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# CHECK: - { id: 4, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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fixedStack:
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- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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body: |
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bb.0:
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%0(p0) = G_FRAME_INDEX %fixed-stack.0
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%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
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%2(p0) = COPY %sp
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%3(s32) = G_CONSTANT i32 8
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%4(p0) = G_GEP %2, %3(s32)
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G_STORE %1(s32), %4(p0) :: (store 4)
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BX_RET 14, _
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...
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---
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name: test_gep
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# CHECK-LABEL: name: test_gep
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb, preferred-register: '' }
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# CHECK: - { id: 1, class: gprb, preferred-register: '' }
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# CHECK: - { id: 2, class: gprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(p0) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(p0) = G_GEP %0, %1(s32)
|
|
%r0 = COPY %2(p0)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_constants
|
|
# CHECK-LABEL: name: test_constants
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
body: |
|
|
bb.0:
|
|
%0(s32) = G_CONSTANT 42
|
|
%r0 = COPY %0(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_globals
|
|
# CHECK-LABEL: name: test_globals
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
body: |
|
|
bb.0:
|
|
%0(p0) = G_GLOBAL_VALUE @a_global
|
|
%r0 = COPY %0(p0)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_anyext_s8_32
|
|
# CHECK-LABEL: name: test_anyext_s8_32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s8) = G_TRUNC %0(s32)
|
|
%2(s32) = G_ANYEXT %1(s8)
|
|
%r0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_anyext_s16_32
|
|
# CHECK-LABEL: name: test_anyext_s16_32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
%2(s32) = G_ANYEXT %1(s16)
|
|
%r0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_trunc_s32_16
|
|
# CHECK-LABEL: name: test_trunc_s32_16
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%2(p0) = COPY %r1
|
|
%1(s16) = G_TRUNC %0(s32)
|
|
G_STORE %1(s16), %2 :: (store 2)
|
|
BX_RET 14, _
|
|
...
|
|
---
|
|
name: test_icmp_eq_s32
|
|
# CHECK-LABEL: name: test_icmp_eq_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
%r0 = COPY %3(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
|
|
...
|
|
---
|
|
name: test_fcmp_one_s32
|
|
# CHECK-LABEL: name: test_fcmp_one_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
%r0 = COPY %3(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
|
|
...
|
|
---
|
|
name: test_fcmp_ugt_s64
|
|
# CHECK-LABEL: name: test_fcmp_ugt_s64
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
%r0 = COPY %3(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
|
|
...
|
|
---
|
|
name: test_select_s32
|
|
# CHECK-LABEL: name: test_select_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s1) = G_TRUNC %2(s32)
|
|
%4(s32) = G_SELECT %3(s1), %0, %1
|
|
%r0 = COPY %4(s32)
|
|
BX_RET 14, _, implicit %r0
|
|
|
|
...
|
|
---
|
|
name: test_br
|
|
# CHECK-LABEL: name: test_br
|
|
legalized: true
|
|
regBankSelected: false
|
|
# CHECK: regBankSelected: true
|
|
selected: false
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
# CHECK: { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: { id: 1, class: gprb, preferred-register: '' }
|
|
# Check that we map the condition of the G_BRCOND into the GPR.
|
|
# For the G_BR, there are no registers to map, but make sure we don't crash.
|
|
body: |
|
|
bb.0:
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
liveins: %r0
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s1) = G_TRUNC %0(s32)
|
|
G_BRCOND %1(s1), %bb.1
|
|
G_BR %bb.2
|
|
|
|
bb.1:
|
|
BX_RET 14, _
|
|
|
|
bb.2:
|
|
BX_RET 14, _
|
|
|
|
...
|
|
---
|
|
name: test_fadd_s32
|
|
# CHECK-LABEL: name: test_fadd_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FADD %0, %1
|
|
%s0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %s0
|
|
|
|
...
|
|
---
|
|
name: test_fadd_s64
|
|
# CHECK-LABEL: name: test_fadd_s64
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FADD %0, %1
|
|
%d0 = COPY %2(s64)
|
|
BX_RET 14, _, implicit %d0
|
|
|
|
...
|
|
---
|
|
name: test_fsub_s32
|
|
# CHECK-LABEL: name: test_fsub_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FSUB %0, %1
|
|
%s0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %s0
|
|
|
|
...
|
|
---
|
|
name: test_fsub_s64
|
|
# CHECK-LABEL: name: test_fsub_s64
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FSUB %0, %1
|
|
%d0 = COPY %2(s64)
|
|
BX_RET 14, _, implicit %d0
|
|
|
|
...
|
|
---
|
|
name: test_fmul_s32
|
|
# CHECK-LABEL: name: test_fmul_s32
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %s0, %s1
|
|
|
|
%0(s32) = COPY %s0
|
|
%1(s32) = COPY %s1
|
|
%2(s32) = G_FMUL %0, %1
|
|
%s0 = COPY %2(s32)
|
|
BX_RET 14, _, implicit %s0
|
|
|
|
...
|
|
---
|
|
name: test_fmul_s64
|
|
# CHECK-LABEL: name: test_fmul_s64
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0, %d1
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s64) = COPY %d1
|
|
%2(s64) = G_FMUL %0, %1
|
|
%d0 = COPY %2(s64)
|
|
BX_RET 14, _, implicit %d0
|
|
|
|
...
|
|
---
|
|
name: test_soft_fp_s64
|
|
# CHECK-LABEL: name: test_soft_fp_s64
|
|
legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
# CHECK: registers:
|
|
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
|
|
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
|
|
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
|
|
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
|
|
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
|
|
%r0 = COPY %3(s32)
|
|
%r1 = COPY %4(s32)
|
|
BX_RET 14, _, implicit %r0, implicit %r1
|
|
|
|
...
|