Daniel Sanders 7fcedd84f2 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. ... Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883		2015-06-27 15:39:19 +00:00
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valid-mips64r6-el.txt	[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.	2015-06-27 15:39:19 +00:00
valid-mips64r6.txt	[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.	2015-06-27 15:39:19 +00:00
valid-xfail-mips64r6.txt	[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.	2015-01-29 11:33:41 +00:00