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625 lines
18 KiB
C++
625 lines
18 KiB
C++
//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise ARM hardware features
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// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMTargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include <cctype>
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using namespace llvm;
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static StringRef getHWDivSynonym(StringRef HWDiv) {
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return StringSwitch<StringRef>(HWDiv)
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.Case("thumb,arm", "arm,thumb")
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.Default(HWDiv);
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}
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// Allows partial match, ex. "v7a" matches "armv7a".
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ARM::ArchKind ARM::parseArch(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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StringRef Syn = getArchSynonym(Arch);
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for (const auto &A : ARCHNames) {
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if (A.getName().endswith(Syn))
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return A.ID;
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}
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return ArchKind::INVALID;
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}
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// Version number (ex. v7 = 7).
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unsigned ARM::parseArchVersion(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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switch (parseArch(Arch)) {
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case ArchKind::ARMV2:
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case ArchKind::ARMV2A:
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return 2;
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case ArchKind::ARMV3:
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case ArchKind::ARMV3M:
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return 3;
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case ArchKind::ARMV4:
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case ArchKind::ARMV4T:
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return 4;
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case ArchKind::ARMV5T:
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case ArchKind::ARMV5TE:
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case ArchKind::IWMMXT:
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case ArchKind::IWMMXT2:
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case ArchKind::XSCALE:
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case ArchKind::ARMV5TEJ:
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return 5;
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case ArchKind::ARMV6:
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case ArchKind::ARMV6K:
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case ArchKind::ARMV6T2:
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case ArchKind::ARMV6KZ:
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case ArchKind::ARMV6M:
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return 6;
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case ArchKind::ARMV7A:
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case ArchKind::ARMV7VE:
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case ArchKind::ARMV7R:
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case ArchKind::ARMV7M:
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case ArchKind::ARMV7S:
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case ArchKind::ARMV7EM:
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case ArchKind::ARMV7K:
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return 7;
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case ArchKind::ARMV8A:
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case ArchKind::ARMV8_1A:
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case ArchKind::ARMV8_2A:
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case ArchKind::ARMV8_3A:
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case ArchKind::ARMV8_4A:
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case ArchKind::ARMV8_5A:
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case ArchKind::ARMV8_6A:
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case ArchKind::ARMV8_7A:
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case ArchKind::ARMV8R:
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case ArchKind::ARMV8MBaseline:
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case ArchKind::ARMV8MMainline:
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case ArchKind::ARMV8_1MMainline:
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return 8;
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case ArchKind::INVALID:
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return 0;
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}
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llvm_unreachable("Unhandled architecture");
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}
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// Profile A/R/M
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ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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switch (parseArch(Arch)) {
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case ArchKind::ARMV6M:
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case ArchKind::ARMV7M:
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case ArchKind::ARMV7EM:
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case ArchKind::ARMV8MMainline:
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case ArchKind::ARMV8MBaseline:
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case ArchKind::ARMV8_1MMainline:
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return ProfileKind::M;
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case ArchKind::ARMV7R:
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case ArchKind::ARMV8R:
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return ProfileKind::R;
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case ArchKind::ARMV7A:
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case ArchKind::ARMV7VE:
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case ArchKind::ARMV7K:
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case ArchKind::ARMV8A:
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case ArchKind::ARMV8_1A:
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case ArchKind::ARMV8_2A:
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case ArchKind::ARMV8_3A:
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case ArchKind::ARMV8_4A:
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case ArchKind::ARMV8_5A:
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case ArchKind::ARMV8_6A:
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case ArchKind::ARMV8_7A:
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return ProfileKind::A;
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case ArchKind::ARMV2:
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case ArchKind::ARMV2A:
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case ArchKind::ARMV3:
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case ArchKind::ARMV3M:
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case ArchKind::ARMV4:
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case ArchKind::ARMV4T:
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case ArchKind::ARMV5T:
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case ArchKind::ARMV5TE:
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case ArchKind::ARMV5TEJ:
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case ArchKind::ARMV6:
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case ArchKind::ARMV6K:
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case ArchKind::ARMV6T2:
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case ArchKind::ARMV6KZ:
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case ArchKind::ARMV7S:
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case ArchKind::IWMMXT:
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case ArchKind::IWMMXT2:
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case ArchKind::XSCALE:
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case ArchKind::INVALID:
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return ProfileKind::INVALID;
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}
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llvm_unreachable("Unhandled architecture");
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}
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StringRef ARM::getArchSynonym(StringRef Arch) {
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return StringSwitch<StringRef>(Arch)
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.Case("v5", "v5t")
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.Case("v5e", "v5te")
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.Case("v6j", "v6")
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.Case("v6hl", "v6k")
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.Cases("v6m", "v6sm", "v6s-m", "v6-m")
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.Cases("v6z", "v6zk", "v6kz")
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.Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
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.Case("v7r", "v7-r")
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.Case("v7m", "v7-m")
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.Case("v7em", "v7e-m")
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.Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
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.Case("v8.1a", "v8.1-a")
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.Case("v8.2a", "v8.2-a")
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.Case("v8.3a", "v8.3-a")
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.Case("v8.4a", "v8.4-a")
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.Case("v8.5a", "v8.5-a")
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.Case("v8.6a", "v8.6-a")
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.Case("v8.7a", "v8.7-a")
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.Case("v8r", "v8-r")
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.Case("v8m.base", "v8-m.base")
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.Case("v8m.main", "v8-m.main")
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.Case("v8.1m.main", "v8.1-m.main")
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.Default(Arch);
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}
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bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
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if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
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return false;
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static const struct FPUFeatureNameInfo {
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const char *PlusName, *MinusName;
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FPUVersion MinVersion;
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FPURestriction MaxRestriction;
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} FPUFeatureInfoList[] = {
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// We have to specify the + and - versions of the name in full so
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// that we can return them as static StringRefs.
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//
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// Also, the SubtargetFeatures ending in just "sp" are listed here
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// under FPURestriction::None, which is the only FPURestriction in
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// which they would be valid (since FPURestriction::SP doesn't
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// exist).
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{"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
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{"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
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{"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
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{"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
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{"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
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{"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None},
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{"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16},
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{"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None},
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{"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
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{"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16},
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{"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None},
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{"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None},
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{"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
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{"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16},
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{"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
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{"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
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{"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
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{"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
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};
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for (const auto &Info: FPUFeatureInfoList) {
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if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
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FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
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Features.push_back(Info.PlusName);
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else
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Features.push_back(Info.MinusName);
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}
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static const struct NeonFeatureNameInfo {
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const char *PlusName, *MinusName;
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NeonSupportLevel MinSupportLevel;
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} NeonFeatureInfoList[] = {
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{"+neon", "-neon", NeonSupportLevel::Neon},
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{"+sha2", "-sha2", NeonSupportLevel::Crypto},
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{"+aes", "-aes", NeonSupportLevel::Crypto},
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};
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for (const auto &Info: NeonFeatureInfoList) {
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if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
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Features.push_back(Info.PlusName);
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else
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Features.push_back(Info.MinusName);
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}
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return true;
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}
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// Little/Big endian
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ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
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if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
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Arch.startswith("aarch64_be"))
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return EndianKind::BIG;
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if (Arch.startswith("arm") || Arch.startswith("thumb")) {
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if (Arch.endswith("eb"))
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return EndianKind::BIG;
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else
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return EndianKind::LITTLE;
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}
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if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
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return EndianKind::LITTLE;
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return EndianKind::INVALID;
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}
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// ARM, Thumb, AArch64
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ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
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return StringSwitch<ISAKind>(Arch)
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.StartsWith("aarch64", ISAKind::AARCH64)
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.StartsWith("arm64", ISAKind::AARCH64)
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.StartsWith("thumb", ISAKind::THUMB)
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.StartsWith("arm", ISAKind::ARM)
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.Default(ISAKind::INVALID);
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}
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unsigned ARM::parseFPU(StringRef FPU) {
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StringRef Syn = getFPUSynonym(FPU);
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for (const auto &F : FPUNames) {
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if (Syn == F.getName())
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return F.ID;
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}
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return FK_INVALID;
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}
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ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return NeonSupportLevel::None;
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return FPUNames[FPUKind].NeonSupport;
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}
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// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
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// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
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// "v.+", if the latter, return unmodified string, minus 'eb'.
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// If invalid, return empty string.
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StringRef ARM::getCanonicalArchName(StringRef Arch) {
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size_t offset = StringRef::npos;
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StringRef A = Arch;
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StringRef Error = "";
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// Begins with "arm" / "thumb", move past it.
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if (A.startswith("arm64_32"))
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offset = 8;
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else if (A.startswith("arm64e"))
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offset = 6;
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else if (A.startswith("arm64"))
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offset = 5;
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else if (A.startswith("aarch64_32"))
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offset = 10;
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else if (A.startswith("arm"))
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offset = 3;
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else if (A.startswith("thumb"))
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offset = 5;
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else if (A.startswith("aarch64")) {
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offset = 7;
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// AArch64 uses "_be", not "eb" suffix.
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if (A.find("eb") != StringRef::npos)
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return Error;
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if (A.substr(offset, 3) == "_be")
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offset += 3;
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}
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// Ex. "armebv7", move past the "eb".
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if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
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offset += 2;
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// Or, if it ends with eb ("armv7eb"), chop it off.
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else if (A.endswith("eb"))
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A = A.substr(0, A.size() - 2);
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// Trim the head
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if (offset != StringRef::npos)
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A = A.substr(offset);
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// Empty string means offset reached the end, which means it's valid.
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if (A.empty())
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return Arch;
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// Only match non-marketing names
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if (offset != StringRef::npos) {
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// Must start with 'vN'.
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if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1])))
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return Error;
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// Can't have an extra 'eb'.
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if (A.find("eb") != StringRef::npos)
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return Error;
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}
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// Arch will either be a 'v' name (v7a) or a marketing name (xscale).
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return A;
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}
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StringRef ARM::getFPUSynonym(StringRef FPU) {
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return StringSwitch<StringRef>(FPU)
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.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
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.Case("vfp2", "vfpv2")
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.Case("vfp3", "vfpv3")
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.Case("vfp4", "vfpv4")
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.Case("vfp3-d16", "vfpv3-d16")
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.Case("vfp4-d16", "vfpv4-d16")
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.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
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.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
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.Case("fp5-sp-d16", "fpv5-sp-d16")
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.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
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// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
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.Case("neon-vfpv3", "neon")
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.Default(FPU);
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}
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StringRef ARM::getFPUName(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return StringRef();
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return FPUNames[FPUKind].getName();
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}
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ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return FPUVersion::NONE;
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return FPUNames[FPUKind].FPUVer;
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}
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ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return FPURestriction::None;
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return FPUNames[FPUKind].Restriction;
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}
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unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
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if (CPU == "generic")
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return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
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return StringSwitch<unsigned>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, DEFAULT_FPU)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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uint64_t ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
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if (CPU == "generic")
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return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
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return StringSwitch<uint64_t>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, \
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ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
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DEFAULT_EXT)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::AEK_INVALID);
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}
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bool ARM::getHWDivFeatures(uint64_t HWDivKind,
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std::vector<StringRef> &Features) {
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if (HWDivKind == AEK_INVALID)
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return false;
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if (HWDivKind & AEK_HWDIVARM)
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Features.push_back("+hwdiv-arm");
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else
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Features.push_back("-hwdiv-arm");
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if (HWDivKind & AEK_HWDIVTHUMB)
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Features.push_back("+hwdiv");
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else
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Features.push_back("-hwdiv");
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return true;
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}
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bool ARM::getExtensionFeatures(uint64_t Extensions,
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std::vector<StringRef> &Features) {
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if (Extensions == AEK_INVALID)
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return false;
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for (const auto &AE : ARCHExtNames) {
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if ((Extensions & AE.ID) == AE.ID && AE.Feature)
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Features.push_back(AE.Feature);
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else if (AE.NegFeature)
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Features.push_back(AE.NegFeature);
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}
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return getHWDivFeatures(Extensions, Features);
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}
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StringRef ARM::getArchName(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getName();
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}
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StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
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}
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StringRef ARM::getSubArch(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
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}
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unsigned ARM::getArchAttr(ARM::ArchKind AK) {
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return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
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}
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StringRef ARM::getArchExtName(uint64_t ArchExtKind) {
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for (const auto &AE : ARCHExtNames) {
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if (ArchExtKind == AE.ID)
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return AE.getName();
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}
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return StringRef();
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}
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static bool stripNegationPrefix(StringRef &Name) {
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if (Name.startswith("no")) {
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Name = Name.substr(2);
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return true;
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}
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return false;
|
|
}
|
|
|
|
StringRef ARM::getArchExtFeature(StringRef ArchExt) {
|
|
bool Negated = stripNegationPrefix(ArchExt);
|
|
for (const auto &AE : ARCHExtNames) {
|
|
if (AE.Feature && ArchExt == AE.getName())
|
|
return StringRef(Negated ? AE.NegFeature : AE.Feature);
|
|
}
|
|
|
|
return StringRef();
|
|
}
|
|
|
|
static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) {
|
|
const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
|
|
|
|
// If the input FPU already supports double-precision, then there
|
|
// isn't any different FPU we can return here.
|
|
//
|
|
// The current available FPURestriction values are None (no
|
|
// restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs
|
|
// and single precision only); there's no value representing
|
|
// SP restriction without D16. So this test just means 'is it
|
|
// SP only?'.
|
|
if (InputFPU.Restriction != ARM::FPURestriction::SP_D16)
|
|
return ARM::FK_INVALID;
|
|
|
|
// Otherwise, look for an FPU entry with all the same fields, except
|
|
// that SP_D16 has been replaced with just D16, representing adding
|
|
// double precision and not changing anything else.
|
|
for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
|
|
if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
|
|
CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
|
|
CandidateFPU.Restriction == ARM::FPURestriction::D16) {
|
|
return CandidateFPU.ID;
|
|
}
|
|
}
|
|
|
|
// nothing found
|
|
return ARM::FK_INVALID;
|
|
}
|
|
|
|
bool ARM::appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
|
|
StringRef ArchExt,
|
|
std::vector<StringRef> &Features,
|
|
unsigned &ArgFPUID) {
|
|
|
|
size_t StartingNumFeatures = Features.size();
|
|
const bool Negated = stripNegationPrefix(ArchExt);
|
|
uint64_t ID = parseArchExt(ArchExt);
|
|
|
|
if (ID == AEK_INVALID)
|
|
return false;
|
|
|
|
for (const auto &AE : ARCHExtNames) {
|
|
if (Negated) {
|
|
if ((AE.ID & ID) == ID && AE.NegFeature)
|
|
Features.push_back(AE.NegFeature);
|
|
} else {
|
|
if ((AE.ID & ID) == AE.ID && AE.Feature)
|
|
Features.push_back(AE.Feature);
|
|
}
|
|
}
|
|
|
|
if (CPU == "")
|
|
CPU = "generic";
|
|
|
|
if (ArchExt == "fp" || ArchExt == "fp.dp") {
|
|
unsigned FPUKind;
|
|
if (ArchExt == "fp.dp") {
|
|
if (Negated) {
|
|
Features.push_back("-fp64");
|
|
return true;
|
|
}
|
|
FPUKind = findDoublePrecisionFPU(getDefaultFPU(CPU, AK));
|
|
} else if (Negated) {
|
|
FPUKind = ARM::FK_NONE;
|
|
} else {
|
|
FPUKind = getDefaultFPU(CPU, AK);
|
|
}
|
|
ArgFPUID = FPUKind;
|
|
return ARM::getFPUFeatures(FPUKind, Features);
|
|
}
|
|
return StartingNumFeatures != Features.size();
|
|
}
|
|
|
|
StringRef ARM::getDefaultCPU(StringRef Arch) {
|
|
ArchKind AK = parseArch(Arch);
|
|
if (AK == ArchKind::INVALID)
|
|
return StringRef();
|
|
|
|
// Look for multiple AKs to find the default for pair AK+Name.
|
|
for (const auto &CPU : CPUNames) {
|
|
if (CPU.ArchID == AK && CPU.Default)
|
|
return CPU.getName();
|
|
}
|
|
|
|
// If we can't find a default then target the architecture instead
|
|
return "generic";
|
|
}
|
|
|
|
uint64_t ARM::parseHWDiv(StringRef HWDiv) {
|
|
StringRef Syn = getHWDivSynonym(HWDiv);
|
|
for (const auto &D : HWDivNames) {
|
|
if (Syn == D.getName())
|
|
return D.ID;
|
|
}
|
|
return AEK_INVALID;
|
|
}
|
|
|
|
uint64_t ARM::parseArchExt(StringRef ArchExt) {
|
|
for (const auto &A : ARCHExtNames) {
|
|
if (ArchExt == A.getName())
|
|
return A.ID;
|
|
}
|
|
return AEK_INVALID;
|
|
}
|
|
|
|
ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
|
|
for (const auto &C : CPUNames) {
|
|
if (CPU == C.getName())
|
|
return C.ArchID;
|
|
}
|
|
return ArchKind::INVALID;
|
|
}
|
|
|
|
void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
|
|
for (const CpuNames<ArchKind> &Arch : CPUNames) {
|
|
if (Arch.ArchID != ArchKind::INVALID)
|
|
Values.push_back(Arch.getName());
|
|
}
|
|
}
|
|
|
|
StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
|
|
StringRef ArchName =
|
|
CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
|
|
|
|
if (TT.isOSBinFormatMachO()) {
|
|
if (TT.getEnvironment() == Triple::EABI ||
|
|
TT.getOS() == Triple::UnknownOS ||
|
|
parseArchProfile(ArchName) == ProfileKind::M)
|
|
return "aapcs";
|
|
if (TT.isWatchABI())
|
|
return "aapcs16";
|
|
return "apcs-gnu";
|
|
} else if (TT.isOSWindows())
|
|
// FIXME: this is invalid for WindowsCE.
|
|
return "aapcs";
|
|
|
|
// Select the default based on the platform.
|
|
switch (TT.getEnvironment()) {
|
|
case Triple::Android:
|
|
case Triple::GNUEABI:
|
|
case Triple::GNUEABIHF:
|
|
case Triple::MuslEABI:
|
|
case Triple::MuslEABIHF:
|
|
return "aapcs-linux";
|
|
case Triple::EABIHF:
|
|
case Triple::EABI:
|
|
return "aapcs";
|
|
default:
|
|
if (TT.isOSNetBSD())
|
|
return "apcs-gnu";
|
|
if (TT.isOSOpenBSD())
|
|
return "aapcs-linux";
|
|
return "aapcs";
|
|
}
|
|
}
|