ShihPo Hung 86074b81a9 [RISCV] Add intrinsics for vcompress instruction ... This patch defines vcompress intrinsics and lower to V instructions. We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com> Differential revision: https://reviews.llvm.org/D93809		2020-12-29 18:38:15 -08:00
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AsmParser	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
Disassembler
MCTargetDesc
TargetInfo
Utils	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
CMakeLists.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Define vmclr.m/vmset.m intrinsics.	2020-12-28 18:57:17 -08:00
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp
RISCVInstrInfo.h
RISCVInstrInfo.td
RISCVInstrInfoA.td
RISCVInstrInfoB.td
RISCVInstrInfoC.td
RISCVInstrInfoD.td
RISCVInstrInfoF.td
RISCVInstrInfoM.td
RISCVInstrInfoV.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrInfoVPseudos.td	[RISCV] Add intrinsics for vcompress instruction	2020-12-29 18:38:15 -08:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Fill out basic integer RVV ISel patterns	2020-12-29 19:32:18 +00:00
RISCVInstrInfoZfh.td
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Pattern-match more vector-splatted constants	2020-12-28 07:11:10 +00:00
RISCVISelDAGToDAG.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVISelLowering.cpp	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
RISCVISelLowering.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp	[RISCV] Basic jump table lowering	2020-12-22 15:05:54 +00:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h