Artem Belevich b6f334a5b3 [NVPTX] Force minimum alignment of 4 for byval arguments of device-side functions. ... Taking address of a byval variable in PTX is legal, but currently runs into miscompilation by ptxas on sm_50+ (NVIDIA issue 1789042). Work around the issue by enforcing minimum alignment on byval arguments of device functions. The change is a no-op on SASS level for sm_3x where ptxas already aligns local copy by at least 4. Differential Revision: https://reviews.llvm.org/D22428 llvm-svn: 275893		2016-07-18 19:54:56 +00:00
..
AArch64	Disable this-return argument forwarding on ARM/AArch64	2016-07-16 07:07:29 +00:00
AMDGPU	AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32	2016-07-18 18:35:05 +00:00
ARM	Revert "[ARM] Skip inline asm memory operands in DAGToDAGISel"	2016-07-18 19:44:01 +00:00
BPF
Generic	Move mempcpy_call.ll to X86 subdirectory	2016-07-13 18:28:45 +00:00
Hexagon	[Hexagon] Handle returning small structures by value	2016-07-18 17:30:41 +00:00
Inputs
Lanai
Mips	[inlineasm] Propagate operand constraints to the backend	2016-07-18 13:17:31 +00:00
MIR	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
MSP430
NVPTX	[NVPTX] Force minimum alignment of 4 for byval arguments of device-side functions.	2016-07-18 19:54:56 +00:00
PowerPC	[PowerPC] Remove redundant direct moves when extracting integers and converting to FP	2016-07-18 15:30:00 +00:00
SPARC
SystemZ
Thumb	[Thumb-1] Select post-increment load and store where possible	2016-07-15 08:03:56 +00:00
Thumb2
WebAssembly
WinEH
X86	[X86][SSE] Regenerate extraction from promotion test	2016-07-18 18:53:15 +00:00
XCore