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80890657b3
Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
79 lines
2.9 KiB
LLVM
79 lines
2.9 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
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@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_andi_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
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%1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
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; CHECK: llvm_mips_andi_b_test:
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; CHECK: ld.b
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; CHECK: andi.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_andi_b_test
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;
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@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_bmnzi_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
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%1 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, i32 25)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_bmnzi_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, i32) nounwind
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; CHECK: llvm_mips_bmnzi_b_test:
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; CHECK: ld.b
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; CHECK: bmnzi.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_bmnzi_b_test
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;
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@llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_bmzi_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
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%1 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, i32 25)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_bmzi_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, i32) nounwind
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; CHECK: llvm_mips_bmzi_b_test:
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; CHECK: ld.b
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; CHECK: bmzi.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_bmzi_b_test
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;
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@llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_bseli_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
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%1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, i32 25)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_bseli_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, i32) nounwind
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; CHECK: llvm_mips_bseli_b_test:
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; CHECK: ld.b
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; CHECK: bseli.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_bseli_b_test
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;
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