Artem Tamazov 7523016960 [AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional. ... Register numbers may be specified as assembly-time expressions. This feature can be useful in macros and alike. However, expressions are supported within sqare braces only. Sqare braces were initially intended to support specifying of multiple (pairs/quads...) registers. Syntax like v[8:8] which specifies single register is also supported. That allows expressions but looks a bit unnatural. This change supports syntax REG[EXPR]. Tests added. Differential Revision: http://reviews.llvm.org/D20588 llvm-svn: 270990		2016-05-27 12:50:13 +00:00
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AMDGPUAsmParser.cpp	[AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional.	2016-05-27 12:50:13 +00:00
CMakeLists.txt	[AMDGPU] Using table-driven amd_kernel_code_t field parser in assembler.	2016-03-06 20:25:36 +00:00
LLVMBuild.txt	AMDGPU/SI: Add hsa code object directives	2015-06-26 21:15:07 +00:00