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ec3a12595c
ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
58 lines
1.8 KiB
LLVM
58 lines
1.8 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
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define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_weak:
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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; CHECK-NEXT: BB#0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK-NEXT: cmp [[LOADED]], r1
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; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#1:
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; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0]
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; CHECK-NEXT: cmp [[SUCCESS]], #0
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; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#2:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[LDFAILBB]]:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: [[FAILBB]]:
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; CHECK-NEXT: str r3, [r0]
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; CHECK-NEXT: bx lr
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store i32 %oldval, i32* %addr
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ret void
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}
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define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_cmpxchg_weak_to_bool:
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%success = extractvalue { i32, i1 } %pair, 1
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; CHECK-NEXT: BB#0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1]
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; CHECK-NEXT: cmp [[LOADED]], r2
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; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]]
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; CHECK-NEXT: BB#1:
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; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1]
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: cmp [[SUCCESS]], #0
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; CHECK-NEXT: bxne lr
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: mov r0, #1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: [[LDFAILBB]]:
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; CHECK-NEXT: clrex
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: bx lr
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ret i1 %success
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}
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