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dd963c2722
Somehow we seem to have ended up without any actual tests of the CodeGen side. Easy enough to fix. llvm-svn: 225930
59 lines
1.5 KiB
LLVM
59 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s
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define i32 @test_crc32b(i32 %cur, i8 %next) {
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; CHECK-LABEL: test_crc32b:
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; CHECK: crc32b r0, r0, r1
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%bits = zext i8 %next to i32
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%val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32h(i32 %cur, i16 %next) {
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; CHECK-LABEL: test_crc32h:
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; CHECK: crc32h r0, r0, r1
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%bits = zext i16 %next to i32
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%val = call i32 @llvm.arm.crc32h(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32w(i32 %cur, i32 %next) {
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; CHECK-LABEL: test_crc32w:
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; CHECK: crc32w r0, r0, r1
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%val = call i32 @llvm.arm.crc32w(i32 %cur, i32 %next)
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ret i32 %val
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}
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define i32 @test_crc32cb(i32 %cur, i8 %next) {
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; CHECK-LABEL: test_crc32cb:
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; CHECK: crc32cb r0, r0, r1
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%bits = zext i8 %next to i32
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%val = call i32 @llvm.arm.crc32cb(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32ch(i32 %cur, i16 %next) {
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; CHECK-LABEL: test_crc32ch:
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; CHECK: crc32ch r0, r0, r1
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%bits = zext i16 %next to i32
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%val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits)
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ret i32 %val
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}
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define i32 @test_crc32cw(i32 %cur, i32 %next) {
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; CHECK-LABEL: test_crc32cw:
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; CHECK: crc32cw r0, r0, r1
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%val = call i32 @llvm.arm.crc32cw(i32 %cur, i32 %next)
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ret i32 %val
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}
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declare i32 @llvm.arm.crc32b(i32, i32)
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declare i32 @llvm.arm.crc32h(i32, i32)
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declare i32 @llvm.arm.crc32w(i32, i32)
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declare i32 @llvm.arm.crc32x(i32, i64)
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declare i32 @llvm.arm.crc32cb(i32, i32)
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declare i32 @llvm.arm.crc32ch(i32, i32)
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declare i32 @llvm.arm.crc32cw(i32, i32)
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declare i32 @llvm.arm.crc32cx(i32, i64)
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