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5a83e46212
This is especially visible in softfp mode, for example in the implementation of libm fabs/fneg functions. If we have: %1 = vmovdrr r0, r1 %2 = fabs %1 then move the fabs before the vmovdrr: %1 = and r1, #0x7FFFFFFF %2 = vmovdrr r0, r1 This is never a lose, and could be a serious win because the vmovdrr may be followed by a vmovrrd, which would enable us to remove the conversion into FPRs completely. We already do this for f32, but not for f64. Tests are added for both. llvm-svn: 246360
42 lines
1.1 KiB
LLVM
42 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK
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; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv7--"
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define double @f(double %a) {
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; CHECK-LABEL: f:
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; CHECK: bfc r1, #31, #1
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; CHECK-NEXT: bx lr
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%x = call double @llvm.fabs.f64(double %a) readnone
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ret double %x
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}
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define float @g(float %a) {
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; CHECK-LABEL: g:
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; CHECK-THUMB: bic r0, r0, #-2147483648
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; CHECK-ARM: bfc r0, #31, #1
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; CHECK-NEXT: bx lr
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%x = call float @llvm.fabs.f32(float %a) readnone
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ret float %x
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}
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define double @h(double %a) {
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; CHECK-LABEL: h:
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; CHECK: eor r1, r1, #-2147483648
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; CHECK-NEXT: bx lr
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%x = fsub nsz double -0.0, %a
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ret double %x
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}
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define float @i(float %a) {
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; CHECK-LABEL: i:
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; CHECK: eor r0, r0, #-2147483648
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; CHECK-NEXT: bx lr
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%x = fsub nsz float -0.0, %a
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ret float %x
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}
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declare double @llvm.fabs.f64(double) readnone
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declare float @llvm.fabs.f32(float) readnone
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