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8174379b38
Patch to allow int8 vectors to be multiplied on the SSE unit instead of being scalarized. The patch sign extends the i8 lanes to i16, uses the SSE2 pmullw multiplication instruction, then packs the lower byte from each result. Differential Revision: http://reviews.llvm.org/D9115 llvm-svn: 235837
212 lines
5.8 KiB
LLVM
212 lines
5.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: vpaddq %ymm
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define <4 x i64> @test_vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = add <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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; CHECK: vpaddd %ymm
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define <8 x i32> @test_vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = add <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vpaddw %ymm
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define <16 x i16> @test_vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = add <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: vpaddb %ymm
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define <32 x i8> @test_vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = add <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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; CHECK: vpsubq %ymm
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define <4 x i64> @test_vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = sub <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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; CHECK: vpsubd %ymm
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define <8 x i32> @test_vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = sub <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vpsubw %ymm
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define <16 x i16> @test_vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = sub <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: vpsubb %ymm
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define <32 x i8> @test_vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = sub <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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; CHECK: vpmulld %ymm
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define <8 x i32> @test_vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
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%x = mul <8 x i32> %i, %j
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ret <8 x i32> %x
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}
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; CHECK: vpmullw %ymm
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define <16 x i16> @test_vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
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%x = mul <16 x i16> %i, %j
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ret <16 x i16> %x
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}
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; CHECK: mul-v16i8
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; CHECK: # BB#0:
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; CHECK-NEXT: vpmovsxbw %xmm1, %ymm1
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; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
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; CHECK-NEXT: vpmullw %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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define <16 x i8> @mul-v16i8(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
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%x = mul <16 x i8> %i, %j
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ret <16 x i8> %x
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}
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; CHECK: mul-v32i8
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; CHECK: # BB#0:
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; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm2
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; CHECK-NEXT: vpmovsxbw %xmm2, %ymm2
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm3
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; CHECK-NEXT: vpmovsxbw %xmm3, %ymm3
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; CHECK-NEXT: vpmullw %ymm2, %ymm3, %ymm2
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; CHECK-NEXT: vextracti128 $1, %ymm2, %xmm3
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; CHECK-NEXT: vpshufb %xmm4, %xmm3, %xmm3
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; CHECK-NEXT: vpshufb %xmm4, %xmm2, %xmm2
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; CHECK-NEXT: vpmovsxbw %xmm1, %ymm1
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; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
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; CHECK-NEXT: vpmullw %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vpshufb %xmm4, %xmm1, %xmm1
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; CHECK-NEXT: vpshufb %xmm4, %xmm0, %xmm0
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; CHECK-NEXT: retq
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define <32 x i8> @mul-v32i8(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
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%x = mul <32 x i8> %i, %j
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ret <32 x i8> %x
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}
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; CHECK: mul-v4i64
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; CHECK: vpmuludq %ymm
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; CHECK-NEXT: vpsrlq $32, %ymm
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; CHECK-NEXT: vpmuludq %ymm
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; CHECK-NEXT: vpsllq $32, %ymm
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; CHECK-NEXT: vpaddq %ymm
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; CHECK-NEXT: vpsrlq $32, %ymm
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; CHECK-NEXT: vpmuludq %ymm
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; CHECK-NEXT: vpsllq $32, %ymm
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; CHECK-NEXT: vpaddq %ymm
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define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
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%x = mul <4 x i64> %i, %j
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ret <4 x i64> %x
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}
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; CHECK: mul_const1
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; CHECK: vpaddd
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; CHECK: ret
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define <8 x i32> @mul_const1(<8 x i32> %x) {
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%y = mul <8 x i32> %x, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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ret <8 x i32> %y
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}
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; CHECK: mul_const2
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; CHECK: vpsllq $2
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; CHECK: ret
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define <4 x i64> @mul_const2(<4 x i64> %x) {
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%y = mul <4 x i64> %x, <i64 4, i64 4, i64 4, i64 4>
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ret <4 x i64> %y
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}
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; CHECK: mul_const3
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; CHECK: vpsllw $3
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; CHECK: ret
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define <16 x i16> @mul_const3(<16 x i16> %x) {
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%y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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ret <16 x i16> %y
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}
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; CHECK: mul_const4
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; CHECK: vpxor
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; CHECK: vpsubq
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; CHECK: ret
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define <4 x i64> @mul_const4(<4 x i64> %x) {
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%y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
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ret <4 x i64> %y
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}
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; CHECK: mul_const5
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; CHECK: vxorps
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; CHECK-NEXT: ret
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define <8 x i32> @mul_const5(<8 x i32> %x) {
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%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %y
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}
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; CHECK: mul_const6
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; CHECK: vpmulld
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; CHECK: ret
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define <8 x i32> @mul_const6(<8 x i32> %x) {
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%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
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ret <8 x i32> %y
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}
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; CHECK: mul_const7
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; CHECK: vpaddq
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; CHECK: vpaddq
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; CHECK: ret
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define <8 x i64> @mul_const7(<8 x i64> %x) {
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%y = mul <8 x i64> %x, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
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ret <8 x i64> %y
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}
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; CHECK: mul_const8
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; CHECK: vpsllw $3
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; CHECK: ret
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define <8 x i16> @mul_const8(<8 x i16> %x) {
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%y = mul <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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ret <8 x i16> %y
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}
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; CHECK: mul_const9
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; CHECK: vpmulld
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; CHECK: ret
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define <8 x i32> @mul_const9(<8 x i32> %x) {
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%y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %y
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}
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; CHECK: mul_const10
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; CHECK: vpmulld
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; CHECK: ret
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define <4 x i32> @mul_const10(<4 x i32> %x) {
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; %x * 0x01010101
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%m = mul <4 x i32> %x, <i32 16843009, i32 16843009, i32 16843009, i32 16843009>
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ret <4 x i32> %m
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}
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; CHECK: mul_const11
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; CHECK: vpmulld
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; CHECK: ret
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define <4 x i32> @mul_const11(<4 x i32> %x) {
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; %x * 0x80808080
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%m = mul <4 x i32> %x, <i32 2155905152, i32 2155905152, i32 2155905152, i32 2155905152>
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ret <4 x i32> %m
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}
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