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80b65c93a4
Identity shuffles, of the form (0, 1, 2, 3, ...) are perfectly OK under MVE (they essentially just become bitcasts). We were not catching that in the existing set of what we considered legal though. On NEON, they would be covered by vext's, but that is not generally available in MVE. This uses ShuffleVectorInst::isIdentityMask which is a little odd to use here but does what we want and prevents us from just rewriting what is the same function. Differential Revision: https://reviews.llvm.org/D68241 llvm-svn: 373446
95 lines
3.3 KiB
LLVM
95 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) {
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; CHECK-LABEL: sext_0246:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) {
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; CHECK-LABEL: sext_1357:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev32.16 q0, q0
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_0246(<8 x i16> %src) {
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; CHECK-LABEL: zext_0246:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) {
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; CHECK-LABEL: zext_1357:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev32.16 q0, q0
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: sext_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: sext_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev16.8 q0, q0
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: zext_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: zext_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev16.8 q0, q0
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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