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ec3a12595c
ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
19 lines
495 B
LLVM
19 lines
495 B
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin -verify-machineinstrs | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs | FileCheck %s -check-prefix=T2
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; rdar://8964854
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define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
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; ARM-LABEL: t:
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; ARM: ldrexb
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; ARM: strexb
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; ARM: clrex
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; T2-LABEL: t:
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; T2: strexb
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; T2: ldrexb
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; T2: clrex
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%tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic monotonic
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%tmp1 = extractvalue { i8, i1 } %tmp0, 0
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ret i8 %tmp1
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}
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