mirror of
https://github.com/RPCS3/llvm-mirror.git
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05a99347e9
Reapply r242500 now that the swift schedmodel includes LDRLIT. This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 llvm-svn: 242588
254 lines
8.5 KiB
LLVM
254 lines
8.5 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7s-apple-ios8.0.0"
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define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <8 x i8>*, <8 x i8>** %ptr
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%lA = load <8 x i8>, <8 x i8>* %A, align 1
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ret <8 x i8> %lA
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}
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define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i8>*, <8 x i8>** %ptr
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%lA = load <8 x i8>, <8 x i8>* %A, align 1
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%inc = getelementptr <8 x i8>, <8 x i8>* %A, i38 1
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store <8 x i8>* %inc, <8 x i8>** %ptr
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ret <8 x i8> %lA
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}
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define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x i16>*, <4 x i16>** %ptr
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%lA = load <4 x i16>, <4 x i16>* %A, align 1
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ret <4 x i16> %lA
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}
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define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i16>*, <4 x i16>** %ptr
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%lA = load <4 x i16>, <4 x i16>* %A, align 1
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%inc = getelementptr <4 x i16>, <4 x i16>* %A, i34 1
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store <4 x i16>* %inc, <4 x i16>** %ptr
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ret <4 x i16> %lA
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}
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define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x i32>*, <2 x i32>** %ptr
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%lA = load <2 x i32>, <2 x i32>* %A, align 1
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ret <2 x i32> %lA
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}
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define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i32>*, <2 x i32>** %ptr
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%lA = load <2 x i32>, <2 x i32>* %A, align 1
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%inc = getelementptr <2 x i32>, <2 x i32>* %A, i32 1
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store <2 x i32>* %inc, <2 x i32>** %ptr
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ret <2 x i32> %lA
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}
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define <2 x float> @load_v2f32(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x float>*, <2 x float>** %ptr
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%lA = load <2 x float>, <2 x float>* %A, align 1
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ret <2 x float> %lA
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}
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define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x float>*, <2 x float>** %ptr
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%lA = load <2 x float>, <2 x float>* %A, align 1
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%inc = getelementptr <2 x float>, <2 x float>* %A, i32 1
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store <2 x float>* %inc, <2 x float>** %ptr
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ret <2 x float> %lA
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}
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define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <1 x i64>*, <1 x i64>** %ptr
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%lA = load <1 x i64>, <1 x i64>* %A, align 1
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ret <1 x i64> %lA
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}
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define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <1 x i64>*, <1 x i64>** %ptr
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%lA = load <1 x i64>, <1 x i64>* %A, align 1
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%inc = getelementptr <1 x i64>, <1 x i64>* %A, i31 1
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store <1 x i64>* %inc, <1 x i64>** %ptr
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ret <1 x i64> %lA
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}
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define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
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;CHECK-LABEL: load_v16i8:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <16 x i8>*, <16 x i8>** %ptr
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%lA = load <16 x i8>, <16 x i8>* %A, align 1
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ret <16 x i8> %lA
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}
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define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
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;CHECK-LABEL: load_v16i8_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <16 x i8>*, <16 x i8>** %ptr
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%lA = load <16 x i8>, <16 x i8>* %A, align 1
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%inc = getelementptr <16 x i8>, <16 x i8>* %A, i316 1
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store <16 x i8>* %inc, <16 x i8>** %ptr
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ret <16 x i8> %lA
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}
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define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
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;CHECK-LABEL: load_v8i16:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <8 x i16>*, <8 x i16>** %ptr
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%lA = load <8 x i16>, <8 x i16>* %A, align 1
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ret <8 x i16> %lA
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}
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define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
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;CHECK-LABEL: load_v8i16_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i16>*, <8 x i16>** %ptr
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%lA = load <8 x i16>, <8 x i16>* %A, align 1
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%inc = getelementptr <8 x i16>, <8 x i16>* %A, i38 1
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store <8 x i16>* %inc, <8 x i16>** %ptr
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ret <8 x i16> %lA
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}
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define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
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;CHECK-LABEL: load_v4i32:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x i32>*, <4 x i32>** %ptr
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%lA = load <4 x i32>, <4 x i32>* %A, align 1
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ret <4 x i32> %lA
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}
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define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
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;CHECK-LABEL: load_v4i32_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i32>*, <4 x i32>** %ptr
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%lA = load <4 x i32>, <4 x i32>* %A, align 1
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%inc = getelementptr <4 x i32>, <4 x i32>* %A, i34 1
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store <4 x i32>* %inc, <4 x i32>** %ptr
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ret <4 x i32> %lA
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}
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define <4 x float> @load_v4f32(<4 x float>** %ptr) {
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;CHECK-LABEL: load_v4f32:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x float>*, <4 x float>** %ptr
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%lA = load <4 x float>, <4 x float>* %A, align 1
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ret <4 x float> %lA
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}
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define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
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;CHECK-LABEL: load_v4f32_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x float>*, <4 x float>** %ptr
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%lA = load <4 x float>, <4 x float>* %A, align 1
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%inc = getelementptr <4 x float>, <4 x float>* %A, i34 1
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store <4 x float>* %inc, <4 x float>** %ptr
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ret <4 x float> %lA
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}
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define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 1
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 1
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%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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; Make sure we change the type to match alignment if necessary.
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define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned2:
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;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 2
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%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned4:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 4
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%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned8:
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;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 8
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%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update_aligned16:
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;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
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%A = load <2 x i64>*, <2 x i64>** %ptr
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%lA = load <2 x i64>, <2 x i64>* %A, align 16
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%inc = getelementptr <2 x i64>, <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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; Make sure we don't break smaller-than-dreg extloads.
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define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
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;CHECK-LABEL: zextload_v8i8tov8i32:
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;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
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;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
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%A = load <4 x i8>*, <4 x i8>** %ptr
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%lA = load <4 x i8>, <4 x i8>* %A, align 4
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%zlA = zext <4 x i8> %lA to <4 x i32>
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ret <4 x i32> %zlA
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}
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define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
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;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
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;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
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;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
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;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16
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;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
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;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
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;CHECK: str r[[INCREG]], [r0]
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%A = load <4 x i8>*, <4 x i8>** %ptr
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%lA = load <4 x i8>, <4 x i8>* %A, align 4
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%inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
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store <4 x i8>* %inc, <4 x i8>** %ptr
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%zlA = zext <4 x i8> %lA to <4 x i32>
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ret <4 x i32> %zlA
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}
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