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47028079f1
This is based on the following equivalences: select(C0 & C1, X, Y) <=> select(C0, select(C1, X, Y), Y) select(C0 | C1, X, Y) <=> select(C0, X, select(C1, X, Y)) Many target cannot perform and/or on the CPU flags and therefore the right side should be choosen to avoid materializign the i1 flags in an integer register. If the target can perform this operation efficiently we normalize to the left form. Differential Revision: http://reviews.llvm.org/D7622 llvm-svn: 231507
53 lines
1.5 KiB
LLVM
53 lines
1.5 KiB
LLVM
; RUN: llc -o - %s | FileCheck %s
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target triple = "x86_64-unknown-unknown"
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; select with and i1/or i1 condition should be implemented as a series of 2
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; cmovs, not by producing two conditions and using and on them.
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define i32 @select_and(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
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; CHECK-LABEL: select_and
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; CHECK-NOT: set
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; CHECK-NOT: and[lb]
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; CHECK-NOT: test
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; CHECK: cmov
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; CHECK: cmov
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%cmp0 = icmp ult i32 %a0, %a1
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%cmp1 = fcmp olt float %a2, %a3
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%and = and i1 %cmp0, %cmp1
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%res = select i1 %and, i32 %a4, i32 %a5
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ret i32 %res
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}
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define i32 @select_or(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
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; select with and i1 condition should be implemented as a series of 2 cmovs, not
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; by producing two conditions and using and on them.
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; CHECK-LABEL: select_or
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; CHECK-NOT: set
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; CHECK-NOT: or[lb]
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; CHECK-NOT: test
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; CHECK: cmov
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; CHECK: cmov
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%cmp0 = icmp ult i32 %a0, %a1
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%cmp1 = fcmp olt float %a2, %a3
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%and = or i1 %cmp0, %cmp1
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%res = select i1 %and, i32 %a4, i32 %a5
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ret i32 %res
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}
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; If one of the conditions is materialized as a 0/1 value anyway, then the
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; sequence of 2 cmovs should not be used.
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@var32 = global i32 0
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define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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; CHECK-LABEL: select_noopt
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; CHECK: cmov
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; CHECK-NOT: cmov
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%cmp0 = icmp ult i32 %a0, %a1
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%cmp1 = icmp ult i32 %a1, %a2
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%or = or i1 %cmp0, %cmp1
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%zero_one = zext i1 %or to i32
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store volatile i32 %zero_one, i32* @var32
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%res = select i1 %or, i32 %a3, i32 %a4
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ret i32 %res
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}
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