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b5caea461d
Summary: If shift amount is a constant value > 64 bit it is handled incorrectly during type legalization and X86 lowering. This patch the type of shift amount argument in function DAGTypeLegalizer::ExpandShiftByConstant from unsigned to APInt. Reviewers: nadav, majnemer, sanjoy, RKSimon Subscribers: RKSimon, llvm-commits Differential Revision: http://reviews.llvm.org/D10767 llvm-svn: 241806
45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=x86-64 | FileCheck %s
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define <2 x i256> @test_shl(<2 x i256> %In) {
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%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
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%Out = shl <2 x i256> %In, %Amt
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ret <2 x i256> %Out
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; CHECK-LABEL: test_shl
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; CHECK: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK: retq
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}
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define <2 x i256> @test_srl(<2 x i256> %In) {
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%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
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%Out = lshr <2 x i256> %In, %Amt
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ret <2 x i256> %Out
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; CHECK-LABEL: test_srl
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; CHECK: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK-NEXT: movq $0
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; CHECK: retq
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}
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define <2 x i256> @test_sra(<2 x i256> %In) {
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%Amt = insertelement <2 x i256> undef, i256 -1, i32 0
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%Out = ashr <2 x i256> %In, %Amt
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ret <2 x i256> %Out
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; CHECK-LABEL: test_sra
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; CHECK: sarq $63
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}
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