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f9f7ca4f85
We have a number of useful lowering strategies for VBROADCAST instructions (both from memory and register element 0) which the 128-bit form of the MOVDDUP instruction can make use of. This patch tweaks lowerVectorShuffleAsBroadcast to enable it to broadcast 2f64 args using MOVDDUP as well. It does require a slight tweak to the lowerVectorShuffleAsBroadcast mechanism as the existing MOVDDUP lowering uses isShuffleEquivalent which can match binary shuffles that can lower to (unary) broadcasts. Differential Revision: http://reviews.llvm.org/D17680 llvm-svn: 262478
60 lines
1.6 KiB
LLVM
60 lines
1.6 KiB
LLVM
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse4.1 | FileCheck %s
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define void @t1(float* %R, <4 x float>* %P1) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movss 12(%ecx), %xmm0
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; CHECK-NEXT: movss %xmm0, (%eax)
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; CHECK-NEXT: retl
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%X = load <4 x float>, <4 x float>* %P1
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%tmp = extractelement <4 x float> %X, i32 3
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store float %tmp, float* %R
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ret void
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}
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define float @t2(<4 x float>* %P1) nounwind {
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; CHECK-LABEL: t2:
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; CHECK: # BB#0:
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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; CHECK-NEXT: movss %xmm0, (%esp)
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; CHECK-NEXT: flds (%esp)
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; CHECK-NEXT: popl %eax
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; CHECK-NEXT: retl
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%X = load <4 x float>, <4 x float>* %P1
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%tmp = extractelement <4 x float> %X, i32 2
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ret float %tmp
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}
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define void @t3(i32* %R, <4 x i32>* %P1) nounwind {
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; CHECK-LABEL: t3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl 12(%ecx), %ecx
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; CHECK-NEXT: movl %ecx, (%eax)
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; CHECK-NEXT: retl
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%X = load <4 x i32>, <4 x i32>* %P1
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%tmp = extractelement <4 x i32> %X, i32 3
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store i32 %tmp, i32* %R
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ret void
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}
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define i32 @t4(<4 x i32>* %P1) nounwind {
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; CHECK-LABEL: t4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl 12(%eax), %eax
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; CHECK-NEXT: retl
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%X = load <4 x i32>, <4 x i32>* %P1
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%tmp = extractelement <4 x i32> %X, i32 3
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ret i32 %tmp
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}
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