mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
b7fb5f7be7
Some ISA's such as microMIPS32(R6) have instructions which are near identical for code generation purposes, e.g. xor and xor16. These instructions take the same value types for operands and return values, have the same instruction predicates and map to the same ISD opcode. (These instructions do differ by register classes.) In such cases, the FastISel generator rejects the instruction definition. This patch borrows the 'FastIselShouldIgnore' bit from rL129692 and enables applying it to an instruction definition. Reviewers: mcrosier Differential Revision: https://reviews.llvm.org/D46953 llvm-svn: 332983
38 lines
1.2 KiB
TableGen
38 lines
1.2 KiB
TableGen
// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===- Define the necessary boilerplate for our test target. --------------===//
|
|
|
|
def MyTargetISA : InstrInfo;
|
|
def MyTarget : Target { let InstructionSet = MyTargetISA; }
|
|
|
|
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
|
|
def R1 : Register<"r0"> { let Namespace = "MyTarget"; }
|
|
def GPR32M : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
|
|
def GPR32MOp : RegisterOperand<GPR32M>;
|
|
|
|
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0, R1)>;
|
|
def GPR32Op : RegisterOperand<GPR32>;
|
|
|
|
class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
|
|
let Namespace = "MyTarget";
|
|
let OutOperandList = OOps;
|
|
let InOperandList = IOps;
|
|
let Pattern = Pat;
|
|
}
|
|
|
|
def HasA : Predicate<"Subtarget->hasA()">;
|
|
|
|
let Predicates = [HasA] in {
|
|
|
|
def ADD : I<(outs GPR32Op:$rd), (ins GPR32Op:$rs, GPR32Op:$rt),
|
|
[(set GPR32Op:$rd, (add GPR32Op:$rs, GPR32Op:$rt))]>;
|
|
|
|
let FastISelShouldIgnore = 1 in
|
|
def ADD_M : I<(outs GPR32MOp:$rd), (ins GPR32MOp:$rs, GPR32MOp:$rt),
|
|
[(set GPR32MOp:$rd, (add GPR32MOp:$rs, GPR32MOp:$rt))]>;
|
|
}
|
|
|
|
// CHECK-NOT: error: Duplicate predicate in FastISel table!
|