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1031830a08
r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186
212 lines
13 KiB
TableGen
212 lines
13 KiB
TableGen
//===-- ARMPredicates.td - ARM Instruction Predicates ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
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AssemblerPredicate<"HasV4TOps", "armv4t">;
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def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
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def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
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AssemblerPredicate<"HasV5TOps", "armv5t">;
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def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
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def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
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AssemblerPredicate<"HasV5TEOps", "armv5te">;
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def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
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AssemblerPredicate<"HasV6Ops", "armv6">;
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def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
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def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
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AssemblerPredicate<"HasV6MOps",
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"armv6m or armv6t2">;
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def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
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AssemblerPredicate<"HasV8MBaselineOps",
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"armv8m.base">;
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def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
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AssemblerPredicate<"HasV8MMainlineOps",
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"armv8m.main">;
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def HasV8_1MMainline : Predicate<"Subtarget->hasV8_1MMainlineOps()">,
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AssemblerPredicate<"HasV8_1MMainlineOps",
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"armv8.1m.main">;
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def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
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AssemblerPredicate<"HasMVEIntegerOps",
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"mve">;
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def HasMVEFloat : Predicate<"Subtarget->hasMVEFloatOps()">,
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AssemblerPredicate<"HasMVEFloatOps",
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"mve.fp">;
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def HasFPRegs : Predicate<"Subtarget->hasFPRegs()">,
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AssemblerPredicate<"FeatureFPRegs",
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"fp registers">;
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def HasFPRegs16 : Predicate<"Subtarget->hasFPRegs16()">,
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AssemblerPredicate<"FeatureFPRegs16",
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"16-bit fp registers">;
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def HasFPRegs64 : Predicate<"Subtarget->hasFPRegs64()">,
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AssemblerPredicate<"FeatureFPRegs64",
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"64-bit fp registers">;
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def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">,
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AssemblerPredicate<"FeatureFPRegs,HasV8_1MMainlineOps",
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"armv8.1m.main with FP or MVE">;
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def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
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AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
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def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
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def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
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AssemblerPredicate<"HasV6KOps", "armv6k">;
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def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
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def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
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AssemblerPredicate<"HasV7Ops", "armv7">;
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def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
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AssemblerPredicate<"HasV8Ops", "armv8">;
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def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
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AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
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def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
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AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
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def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
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AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
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def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">,
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AssemblerPredicate<"HasV8_3aOps", "armv8.3a">;
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def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">,
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AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
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def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">,
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AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
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def NoVFP : Predicate<"!Subtarget->hasVFP2Base()">;
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def HasVFP2 : Predicate<"Subtarget->hasVFP2Base()">,
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AssemblerPredicate<"FeatureVFP2_SP", "VFP2">;
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def HasVFP3 : Predicate<"Subtarget->hasVFP3Base()">,
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AssemblerPredicate<"FeatureVFP3_D16_SP", "VFP3">;
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def HasVFP4 : Predicate<"Subtarget->hasVFP4Base()">,
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AssemblerPredicate<"FeatureVFP4_D16_SP", "VFP4">;
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def HasDPVFP : Predicate<"Subtarget->hasFP64()">,
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AssemblerPredicate<"FeatureFP64",
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"double precision VFP">;
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def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8Base()">,
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AssemblerPredicate<"FeatureFPARMv8_D16_SP", "FPARMv8">;
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def HasNEON : Predicate<"Subtarget->hasNEON()">,
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AssemblerPredicate<"FeatureNEON", "NEON">;
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def HasSHA2 : Predicate<"Subtarget->hasSHA2()">,
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AssemblerPredicate<"FeatureSHA2", "sha2">;
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def HasAES : Predicate<"Subtarget->hasAES()">,
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AssemblerPredicate<"FeatureAES", "aes">;
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def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
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AssemblerPredicate<"FeatureCrypto", "crypto">;
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def HasDotProd : Predicate<"Subtarget->hasDotProd()">,
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AssemblerPredicate<"FeatureDotProd", "dotprod">;
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def HasCRC : Predicate<"Subtarget->hasCRC()">,
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AssemblerPredicate<"FeatureCRC", "crc">;
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def HasRAS : Predicate<"Subtarget->hasRAS()">,
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AssemblerPredicate<"FeatureRAS", "ras">;
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def HasLOB : Predicate<"Subtarget->hasLOB()">,
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AssemblerPredicate<"FeatureLOB", "lob">;
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def HasFP16 : Predicate<"Subtarget->hasFP16()">,
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AssemblerPredicate<"FeatureFP16","half-float conversions">;
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def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
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AssemblerPredicate<"FeatureFullFP16","full half-float">;
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def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">,
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AssemblerPredicate<"FeatureFP16FML","full half-float fml">;
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def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">,
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AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">;
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def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
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AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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AssemblerPredicate<"FeatureDSP", "dsp">;
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def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
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AssemblerPredicate<"FeatureDB",
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"data-barriers">;
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def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">,
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AssemblerPredicate<"FeatureDFB",
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"full-data-barrier">;
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def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">,
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AssemblerPredicate<"FeatureV7Clrex",
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"v7 clrex">;
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def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">,
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AssemblerPredicate<"FeatureAcquireRelease",
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"acquire/release">;
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def HasMP : Predicate<"Subtarget->hasMPExtension()">,
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AssemblerPredicate<"FeatureMP",
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"mp-extensions">;
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def HasVirtualization: Predicate<"false">,
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AssemblerPredicate<"FeatureVirtualization",
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"virtualization-extensions">;
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def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
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AssemblerPredicate<"FeatureTrustZone",
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"TrustZone">;
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def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">,
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AssemblerPredicate<"Feature8MSecExt",
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"ARMv8-M Security Extensions">;
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def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
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def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
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def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
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def IsThumb : Predicate<"Subtarget->isThumb()">,
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AssemblerPredicate<"ModeThumb", "thumb">;
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def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
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def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
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AssemblerPredicate<"ModeThumb,FeatureThumb2",
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"thumb2">;
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def IsMClass : Predicate<"Subtarget->isMClass()">,
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AssemblerPredicate<"FeatureMClass", "armv*m">;
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def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
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AssemblerPredicate<"!FeatureMClass",
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"!armv*m">;
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def IsARM : Predicate<"!Subtarget->isThumb()">,
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AssemblerPredicate<"!ModeThumb", "arm-mode">;
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def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
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def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
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def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
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def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
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def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
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def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">;
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def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">;
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def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
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AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
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def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
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def UseNegativeImmediates :
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Predicate<"false">,
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AssemblerPredicate<"!FeatureNoNegativeImmediates",
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"NegativeImmediates">;
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// FIXME: Eventually this will be just "hasV6T2Ops".
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let RecomputePerFunction = 1 in {
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def UseMovt : Predicate<"Subtarget->useMovt()">;
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def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
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def UseMovtInPic : Predicate<"Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()">;
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def DontUseMovtInPic : Predicate<"!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()">;
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def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&"
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" TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||"
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"Subtarget->hasMinSize())">;
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}
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def UseMulOps : Predicate<"Subtarget->useMulOps()">;
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// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
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// But only select them if more precision in FP computation is allowed, and when
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// they are not slower than a mul + add sequence.
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// Do not use them for Darwin platforms.
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def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
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" FPOpFusion::Fast && "
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" Subtarget->hasVFP4Base()) && "
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"!Subtarget->isTargetDarwin() &&"
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"Subtarget->useFPVMLx()">;
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def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;
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def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;
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def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;
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def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;
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def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"
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"!Subtarget->useNEONForSinglePrecisionFP()">;
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def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
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"Subtarget->useNEONForSinglePrecisionFP()">;
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let RecomputePerFunction = 1 in {
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def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
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def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
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}
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def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
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// Armv8.5-A extensions
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def HasSB : Predicate<"Subtarget->hasSB()">,
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AssemblerPredicate<"FeatureSB", "sb">;
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