Guillaume Chatelet 8109fb5dfe [Alignment][NFC] Use Align for TargetFrameLowering/Subtarget ... Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68993 llvm-svn: 375084		2019-10-17 07:49:39 +00:00
..
AsmParser	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
Disassembler	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
MCTargetDesc	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
TargetInfo
Utils	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
CMakeLists.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
LLVMBuild.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.td	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallLowering.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVFrameLowering.cpp	[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore	2019-10-04 02:00:57 +00:00
RISCVFrameLowering.h	[Alignment][NFC] Use Align for TargetFrameLowering/Subtarget	2019-10-17 07:49:39 +00:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
RISCVInstrInfo.h	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
RISCVInstrInfo.td	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
RISCVInstrInfoA.td	Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"	2019-09-19 16:26:14 +00:00
RISCVInstrInfoC.td	[RISCV] Added missing ImmLeaf predicates	2019-10-04 23:42:07 +00:00
RISCVInstrInfoD.td
RISCVInstrInfoF.td	[RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)	2019-10-03 15:47:28 +00:00
RISCVInstrInfoM.td
RISCVInstructionSelector.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Fix static analysis issues	2019-09-20 13:48:02 +00:00
RISCVISelLowering.cpp	[RISCV] Support fast calling convention	2019-10-15 02:04:29 +00:00
RISCVISelLowering.h	[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall	2019-08-28 23:40:37 +00:00
RISCVLegalizerInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVRegisterInfo.h	[RISCV] Implement RISCVRegisterInfo::getPointerRegClass	2019-08-27 21:37:57 +00:00
RISCVRegisterInfo.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVSubtarget.cpp	[RISCV] Add MachineInstr immediate verification	2019-10-16 15:06:02 +00:00
RISCVSubtarget.h	[RISCV] Switch to the Machine Scheduler	2019-09-17 11:15:35 +00:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h