Luis Marques bc3e25486a [RISCV] Rename FPRs and use Register arithmetic ... The new names for FPRs ensure that the Register values within the same class are enumerated consecutively (the order is determined by the `LessRecordRegister` function object). Where there were tables mapping between 32- and 64-bit FPRs (and vice versa) this patch replaces them with Register arithmetic. The enumeration order between different register classes is expected to continue to be arbitrary, although it does impact the conversion from the (overloaded) asm FPR names to Register values, and therefore might require updates to the target if the sorting algorithm is changed. Static asserts were added to ensure that changes to the ordering that would impact the current implementation are detected. Differential Revision: https://reviews.llvm.org/D67423 llvm-svn: 373096		2019-09-27 15:49:10 +00:00
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CMakeLists.txt
LLVMBuild.txt
RISCVDisassembler.cpp	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00