Michael Kuperstein 812c46b9de [X86] Combine vector anyext + and into a vector zext ... Vector zext tends to get legalized into a vector anyext, represented as a vector shuffle with an undef vector + a bitcast, that gets ANDed with a mask that zeroes the undef elements. Combine this into an explicit shuffle with a zero vector instead. This allows shuffle lowering to match it as a zext, instead of matching it as an anyext and emitting an explicit AND. This combine only covers a subset of the cases, but it's a start. Differential Revision: http://reviews.llvm.org/D7666 llvm-svn: 229480		2015-02-17 08:22:51 +00:00
..
AArch64	AArch64: Safely handle the incoming sret call argument.	2015-02-16 18:10:47 +00:00
ARM
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC	2015-02-13 17:51:27 +00:00
MSP430
NVPTX
PowerPC	Move ABI handling and 64-bitness to the PowerPC target machine.	2015-02-17 06:45:15 +00:00
R600	R600/SI: Implement correct f64 fdiv	2015-02-14 04:30:08 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ
Thumb
Thumb2
X86	[X86] Combine vector anyext + and into a vector zext	2015-02-17 08:22:51 +00:00
XCore