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812ee5bc7c
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
66 lines
2.3 KiB
LLVM
66 lines
2.3 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
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%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
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@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
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@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
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@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
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define i32* @t1() nounwind {
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entry:
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; ARM: t1
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; THUMB: t1
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
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; ARM: add r0, r0, #124
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; THUMB: adds r0, #124
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t2() nounwind {
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entry:
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; ARM: t2
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; THUMB: t2
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
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; ARM: movw [[R:r[0-9]+]], #1148
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; ARM: add r0, r{{[0-9]+}}, [[R]]
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; THUMB: addw r0, r0, #1148
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t3() nounwind {
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entry:
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; ARM: t3
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; THUMB: t3
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
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; ARM: add r0, r0, #140
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; THUMB: adds r0, #140
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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define i32* @t4() nounwind {
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entry:
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; ARM: t4
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; THUMB: t4
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
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; ARM-NOT: movw r{{[0-9]}}, #1060
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #132
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #24
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #36
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #24
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; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4
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; ARM: movw r{{[0-9]}}, #1284
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; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284
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%0 = load i32** %addr, align 4
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ret i32* %0
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}
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