Evan Cheng 817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. ... llvm-svn: 78030		2009-08-04 01:41:15 +00:00
..
Alpha	Make promotion in operation legalization for SETCC work correctly.	2009-07-17 05:16:04 +00:00
ARM	Lower CONCAT_VECTOR during legalization instead of matching it during isel.	2009-08-03 20:36:38 +00:00
Blackfin	Remove unneeded intrinsics from Blackfin backend.	2009-08-02 21:49:05 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Add some generic expansion logic for SMULO and UMULO. Fixes UMULO	2009-06-16 06:58:29 +00:00
CPP
Generic	Remove the IA-64 backend.	2009-07-24 00:30:09 +00:00
Mips	Pass target triple string in to TargetMachine constructor.	2009-08-03 04:03:51 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PIC16	Test case to check that separate section is created for a global variable specified with section attribute.	2009-07-27 16:20:41 +00:00
PowerPC	Revert r75663 (and r76805), as it is causing regressions on powerpc.	2009-07-23 00:09:46 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
SystemZ	convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"	2009-07-21 17:36:24 +00:00
Thumb	tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.	2009-07-28 07:38:35 +00:00
Thumb2	Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.	2009-08-04 01:41:15 +00:00
X86	Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers.	2009-08-03 08:12:53 +00:00
XCore	Add extra SEXT pattern.	2009-08-02 22:45:24 +00:00