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106 lines
3.7 KiB
Plaintext
106 lines
3.7 KiB
Plaintext
//===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
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Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
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registers, to generate better spill code.
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//===----------------------------------------------------------------------===//
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The first should be a single lvx from the constant pool, the second should be
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a xor/stvx:
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void foo(void) {
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int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 17, 1, 1, 1, 1 };
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bar (x);
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}
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#include <string.h>
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void foo(void) {
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int x[8] __attribute__((aligned(128)));
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memset (x, 0, sizeof (x));
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bar (x);
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}
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//===----------------------------------------------------------------------===//
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Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
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When -ffast-math is on, we can use 0.0.
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//===----------------------------------------------------------------------===//
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Consider this:
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v4f32 Vector;
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v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
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Since we know that "Vector" is 16-byte aligned and we know the element offset
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of ".X", we should change the load into a lve*x instruction, instead of doing
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a load/store/lve*x sequence.
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//===----------------------------------------------------------------------===//
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FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
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//===----------------------------------------------------------------------===//
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For functions that use altivec AND have calls, we are VRSAVE'ing all call
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clobbered regs.
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//===----------------------------------------------------------------------===//
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Implement passing vectors by value.
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//===----------------------------------------------------------------------===//
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GCC apparently tries to codegen { C1, C2, Variable, C3 } as a constant pool load
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of C1/C2/C3, then a load and vperm of Variable.
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//===----------------------------------------------------------------------===//
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We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
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aligned stack slot, followed by a load/vperm. We should probably just store it
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to a scalar stack slot, then use lvsl/vperm to load it. If the value is already
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in memory, this is a huge win.
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//===----------------------------------------------------------------------===//
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Do not generate the MFCR/RLWINM sequence for predicate compares when the
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predicate compare is used immediately by a branch. Just branch on the right
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cond code on CR6.
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//===----------------------------------------------------------------------===//
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We need a way to teach tblgen that some operands of an intrinsic are required to
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be constants. The verifier should enforce this constraint.
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//===----------------------------------------------------------------------===//
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Implement multiply for vector integer types, to avoid the horrible scalarized
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code produced by legalize.
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void test(vector int *X, vector int *Y) {
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*X = *X * *Y;
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}
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//===----------------------------------------------------------------------===//
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extract_vector_elt of an arbitrary constant vector can be done with the
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following instructions:
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vTemp = vec_splat(v0,2); // 2 is the element the src is in.
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vec_ste(&destloc,0,vTemp);
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We can do an arbitrary non-constant value by using lvsr/perm/ste.
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//===----------------------------------------------------------------------===//
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If we want to tie instruction selection into the scheduler, we can do some
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constant formation with different instructions. For example, we can generate
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"vsplti -1" with "vcmpequw R,R" and 1,1,1,1 with "vsubcuw R,R", both of which
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use different execution units, thus could help scheduling.
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This is probably only reasonable for a post-pass scheduler.
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//===----------------------------------------------------------------------===//
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