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llvm-mirror/lib/Target/RISCV
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Kamlesh Kumar d4b36a975d [RISCV64] Emit correct lib call for fp(float/double) to ui/si 
Since i32 is not legal in riscv64,
it always promoted to i64 before emitting lib call and
for conversions like float/double to int and float/double to unsigned int
wrong lib call was emitted. This commit fix it using custom lowering.

Differential Revision: https://reviews.llvm.org/D80526
2020-06-18 19:34:16 +05:30
..
AsmParser
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
Disassembler
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
MCTargetDesc
[MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset
2020-05-22 15:47:26 -07:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
CMakeLists.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
LLVMBuild.txt
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCV.td
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVAsmPrinter.cpp
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVCallLowering.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVExpandPseudoInsts.cpp
[RISCV] Use addi rather than add x0
2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp
[MC] Change MCCFIInstruction::createDefCfaOffset to cfiDefCfaOffset which does not negate Offset
2020-05-22 17:07:11 -07:00
RISCVFrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
RISCVInstrFormats.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
…
RISCVInstrInfo.cpp
[MachineOutliner] Teach outliner to set live-ins
2020-04-22 14:19:26 -07:00
RISCVInstrInfo.h
[NFC] unsigned->Register in storeRegTo/loadRegFromStack
2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td
[RISCV] Add instruction definition for dret
2020-04-24 13:27:43 -07:00
RISCVInstrInfoA.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoB.td
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVInstrInfoC.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoF.td
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
RISCVISelDAGToDAG.h
[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp
2020-04-01 11:30:21 +08:00
RISCVISelLowering.cpp
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
2020-06-18 19:34:16 +05:30
RISCVISelLowering.h
[RISCV] Make visibility of overridden methods in RISCVISelLowering match the parent
2020-06-10 09:16:09 +01:00
RISCVLegalizerInfo.cpp
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
RISCVMCInstLower.cpp
[RISCV] Add lowering of global TLS addresses
2019-06-19 08:40:59 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Convert registers from unsigned to Register
2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVSchedRocket32.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSchedule.td
[RISCV] Add new SchedRead SchedWrite
2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVSubtarget.h
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
2020-04-09 18:04:22 +01:00
RISCVSystemOperands.td
[RISCV] Update debug scratch register names
2020-05-05 08:46:07 -07:00
RISCVTargetMachine.cpp
[RISCV] Check the target-abi module flag matches the option
2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00
RISCVTargetTransformInfo.h
[NFC][CostModel] Add TargetCostKind to relevant APIs
2020-05-05 10:35:54 +01:00