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81a9bfe915
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
87 lines
4.4 KiB
LLVM
87 lines
4.4 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
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; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
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; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
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; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
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; DEFAULT-LABEL: {{^}}main:
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; DEFAULT: s_load_dwordx4
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; DEFAULT: s_load_dwordx4
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; DEFAULT: s_waitcnt vmcnt(0)
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; DEFAULT: exp
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; DEFAULT: s_waitcnt lgkmcnt(0)
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; DEFAULT: s_endpgm
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define amdgpu_vs void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) {
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main_body:
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%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0
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%tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
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%tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6)
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%tmp12 = extractelement <4 x float> %tmp11, i32 0
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%tmp13 = extractelement <4 x float> %tmp11, i32 1
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call void @llvm.amdgcn.s.barrier() #1
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%tmp14 = extractelement <4 x float> %tmp11, i32 2
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; %tmp15 = extractelement <4 x float> %tmp11, i32 3
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%tmp15 = load float, float addrspace(2)* %constptr, align 4 ; Force waiting for expcnt and lgkmcnt
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%tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 1
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%tmp17 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp16, !tbaa !0
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%tmp18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp17, i32 0, i32 %arg6)
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%tmp19 = extractelement <4 x float> %tmp18, i32 0
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%tmp20 = extractelement <4 x float> %tmp18, i32 1
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%tmp21 = extractelement <4 x float> %tmp18, i32 2
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%tmp22 = extractelement <4 x float> %tmp18, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %tmp19, float %tmp20, float %tmp21, float %tmp22)
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp12, float %tmp13, float %tmp14, float %tmp15)
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ret void
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}
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; ILPMAX-LABEL: {{^}}main2:
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; ILPMAX: s_load_dwordx4
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; ILPMAX: s_waitcnt lgkmcnt(0)
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; ILPMAX: buffer_load
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; ILPMAX: s_load_dwordx4
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; ILPMAX: s_waitcnt lgkmcnt(0)
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; ILPMAX: buffer_load
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; ILPMAX: s_waitcnt vmcnt(1)
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; ILPMAX: s_waitcnt vmcnt(0)
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; ILPMAX: s_endpgm
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define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)*
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byval, i32 inreg, i32 inreg, i32, i32, i32, i32) {
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main_body:
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%11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0
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%12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0
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%13 = add i32 %5, %7
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%14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13)
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%15 = extractelement <4 x float> %14, i32 0
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%16 = extractelement <4 x float> %14, i32 1
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%17 = extractelement <4 x float> %14, i32 2
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%18 = extractelement <4 x float> %14, i32 3
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%19 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 1
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%20 = load <16 x i8>, <16 x i8> addrspace(2)* %19, align 16, !tbaa !0
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%21 = add i32 %5, %7
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%22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %20, i32 0, i32 %21)
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%23 = extractelement <4 x float> %22, i32 0
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%24 = extractelement <4 x float> %22, i32 1
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%25 = extractelement <4 x float> %22, i32 2
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%26 = extractelement <4 x float> %22, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %15, float %16, float %17, float %18)
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call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %23, float %24, float %25, float %26)
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ret void
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}
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; Function Attrs: convergent nounwind
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declare void @llvm.amdgcn.s.barrier() #1
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #2
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", !2}
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!2 = !{!"tbaa root"}
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