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8a358b3669
This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s llvm-svn: 159525
89 lines
2.7 KiB
TableGen
89 lines
2.7 KiB
TableGen
// RUN: llvm-tblgen %s | grep "\[(set" | count 2
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// RUN: llvm-tblgen %s | grep "\[\]" | count 2
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// XFAIL: vg_leak
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class ValueType<int size, int value> {
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int Size = size;
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int Value = value;
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}
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def f32 : ValueType<32, 1>; // 2 x i64 vector value
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class Intrinsic<string name> {
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string Name = name;
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}
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class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
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list<dag> pattern> {
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bits<8> Opcode = opcode;
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dag OutOperands = oopnds;
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dag InOperands = iopnds;
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string AssemblyString = asmstr;
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list<dag> Pattern = pattern;
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}
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def ops;
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def outs;
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def ins;
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def set;
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// Define registers
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class Register<string n> {
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string Name = n;
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}
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class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
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list<ValueType> RegTypes = regTypes;
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list<Register> MemberList = regList;
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}
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def XMM0: Register<"xmm0">;
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def XMM1: Register<"xmm1">;
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def XMM2: Register<"xmm2">;
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def XMM3: Register<"xmm3">;
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def XMM4: Register<"xmm4">;
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def XMM5: Register<"xmm5">;
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def XMM6: Register<"xmm6">;
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def XMM7: Register<"xmm7">;
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def XMM8: Register<"xmm8">;
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def XMM9: Register<"xmm9">;
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def XMM10: Register<"xmm10">;
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def XMM11: Register<"xmm11">;
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def XMM12: Register<"xmm12">;
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def XMM13: Register<"xmm13">;
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def XMM14: Register<"xmm14">;
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def XMM15: Register<"xmm15">;
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def FR32 : RegisterClass<[f32],
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11,
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XMM12, XMM13, XMM14, XMM15]>;
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class SDNode {}
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def not : SDNode;
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multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
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def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,patterns[0])>;
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def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
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}
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multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
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def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,patterns[0])>;
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def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(asmstr, "\t$dst, $src"),
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!if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
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}
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multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
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scalar<opcode, asmstr, patterns>,
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vscalar<opcode, asmstr, patterns>;
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defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>;
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