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34658dca78
- Rewrite/merge pseudo-atomic instruction emitters to address the
following issue:
* Reduce one unnecessary load in spin-loop
previously the spin-loop looks like
thisMBB:
newMBB:
ld t1 = [bitinstr.addr]
op t2 = t1, [bitinstr.val]
not t3 = t2 (if Invert)
mov EAX = t1
lcs dest = [bitinstr.addr], t3 [EAX is implicit]
bz newMBB
fallthrough -->nextMBB
the 'ld' at the beginning of newMBB should be lift out of the loop
as lcs (or CMPXCHG on x86) will load the current memory value into
EAX. This loop is refined as:
thisMBB:
EAX = LOAD [MI.addr]
mainMBB:
t1 = OP [MI.val], EAX
LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
JNE mainMBB
sinkMBB:
* Remove immopc as, so far, all pseudo-atomic instructions has
all-register form only, there is no immedidate operand.
* Remove unnecessary attributes/modifiers in pseudo-atomic instruction
td
* Fix issues in PR13458
- Add comprehensive tests on atomic ops on various data types.
NOTE: Some of them are turned off due to missing functionality.
- Revise tests due to the new spin-loop generated.
llvm-svn: 164281
251 lines
5.3 KiB
LLVM
251 lines
5.3 KiB
LLVM
; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 | FileCheck %s --check-prefix X64
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; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 | FileCheck %s --check-prefix X32
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@sc32 = external global i32
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define void @atomic_fetch_add32() nounwind {
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; X64: atomic_fetch_add32
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; X32: atomic_fetch_add32
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entry:
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; 32-bit
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%t1 = atomicrmw add i32* @sc32, i32 1 acquire
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; X64: lock
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; X64: incl
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; X32: lock
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; X32: incl
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%t2 = atomicrmw add i32* @sc32, i32 3 acquire
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; X64: lock
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; X64: addl $3
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; X32: lock
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; X32: addl $3
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%t3 = atomicrmw add i32* @sc32, i32 5 acquire
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; X64: lock
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; X64: xaddl
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; X32: lock
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; X32: xaddl
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%t4 = atomicrmw add i32* @sc32, i32 %t3 acquire
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; X64: lock
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; X64: addl
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; X32: lock
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; X32: addl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_sub32() nounwind {
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; X64: atomic_fetch_sub32
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; X32: atomic_fetch_sub32
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%t1 = atomicrmw sub i32* @sc32, i32 1 acquire
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; X64: lock
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; X64: decl
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; X32: lock
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; X32: decl
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%t2 = atomicrmw sub i32* @sc32, i32 3 acquire
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; X64: lock
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; X64: subl $3
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; X32: lock
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; X32: subl $3
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%t3 = atomicrmw sub i32* @sc32, i32 5 acquire
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; X64: lock
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; X64: xaddl
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; X32: lock
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; X32: xaddl
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%t4 = atomicrmw sub i32* @sc32, i32 %t3 acquire
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; X64: lock
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; X64: subl
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; X32: lock
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; X32: subl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_and32() nounwind {
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; X64: atomic_fetch_and32
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; X32: atomic_fetch_and32
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%t1 = atomicrmw and i32* @sc32, i32 3 acquire
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; X64: lock
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; X64: andl $3
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; X32: lock
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; X32: andl $3
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%t2 = atomicrmw and i32* @sc32, i32 5 acquire
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; X64: andl
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; X64: lock
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; X64: cmpxchgl
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; X32: andl
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; X32: lock
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; X32: cmpxchgl
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%t3 = atomicrmw and i32* @sc32, i32 %t2 acquire
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; X64: lock
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; X64: andl
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; X32: lock
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; X32: andl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_or32() nounwind {
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; X64: atomic_fetch_or32
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; X32: atomic_fetch_or32
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%t1 = atomicrmw or i32* @sc32, i32 3 acquire
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; X64: lock
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; X64: orl $3
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; X32: lock
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; X32: orl $3
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%t2 = atomicrmw or i32* @sc32, i32 5 acquire
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; X64: orl
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; X64: lock
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; X64: cmpxchgl
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; X32: orl
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; X32: lock
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; X32: cmpxchgl
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%t3 = atomicrmw or i32* @sc32, i32 %t2 acquire
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; X64: lock
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; X64: orl
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; X32: lock
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; X32: orl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_xor32() nounwind {
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; X64: atomic_fetch_xor32
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; X32: atomic_fetch_xor32
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%t1 = atomicrmw xor i32* @sc32, i32 3 acquire
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; X64: lock
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; X64: xorl $3
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; X32: lock
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; X32: xorl $3
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%t2 = atomicrmw xor i32* @sc32, i32 5 acquire
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; X64: xorl
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; X64: lock
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; X64: cmpxchgl
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; X32: xorl
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; X32: lock
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; X32: cmpxchgl
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%t3 = atomicrmw xor i32* @sc32, i32 %t2 acquire
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; X64: lock
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; X64: xorl
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; X32: lock
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; X32: xorl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_nand32(i32 %x) nounwind {
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; X64: atomic_fetch_nand32
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; X32: atomic_fetch_nand32
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%t1 = atomicrmw nand i32* @sc32, i32 %x acquire
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; X64: andl
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; X64: notl
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; X64: lock
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; X64: cmpxchgl
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; X32: andl
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; X32: notl
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_max32(i32 %x) nounwind {
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%t1 = atomicrmw max i32* @sc32, i32 %x acquire
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; X64: cmpl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgl
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; X32: cmpl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_min32(i32 %x) nounwind {
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%t1 = atomicrmw min i32* @sc32, i32 %x acquire
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; X64: cmpl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgl
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; X32: cmpl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_umax32(i32 %x) nounwind {
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%t1 = atomicrmw umax i32* @sc32, i32 %x acquire
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; X64: cmpl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgl
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; X32: cmpl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_umin32(i32 %x) nounwind {
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%t1 = atomicrmw umin i32* @sc32, i32 %x acquire
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; X64: cmpl
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; X64: cmov
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; X64: lock
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; X64: cmpxchgl
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; X32: cmpl
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; X32: cmov
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_cmpxchg32() nounwind {
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%t1 = cmpxchg i32* @sc32, i32 0, i32 1 acquire
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; X64: lock
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; X64: cmpxchgl
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; X32: lock
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; X32: cmpxchgl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_store32(i32 %x) nounwind {
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store atomic i32 %x, i32* @sc32 release, align 4
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; X64-NOT: lock
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; X64: movl
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; X32-NOT: lock
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; X32: movl
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ret void
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; X64: ret
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; X32: ret
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}
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define void @atomic_fetch_swap32(i32 %x) nounwind {
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%t1 = atomicrmw xchg i32* @sc32, i32 %x acquire
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; X64-NOT: lock
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; X64: xchgl
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; X32-NOT: lock
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; X32: xchgl
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ret void
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; X64: ret
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; X32: ret
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}
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