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94213533f7
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. llvm-svn: 172968
110 lines
2.4 KiB
LLVM
Executable File
110 lines
2.4 KiB
LLVM
Executable File
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: trunc4
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; CHECK: vpermd
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <4 x i32> @trunc4(<4 x i64> %A) nounwind {
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%B = trunc <4 x i64> %A to <4 x i32>
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ret <4 x i32>%B
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}
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; CHECK: trunc8
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; CHECK: vpshufb
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <8 x i16> @trunc8(<8 x i32> %A) nounwind {
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%B = trunc <8 x i32> %A to <8 x i16>
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ret <8 x i16>%B
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}
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; CHECK: sext4
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; CHECK: vpmovsxdq
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <4 x i64> @sext4(<4 x i32> %A) nounwind {
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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; CHECK: sext8
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; CHECK: vpmovsxwd
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <8 x i32> @sext8(<8 x i16> %A) nounwind {
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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; CHECK: zext4
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; CHECK: vpmovzxdq
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <4 x i64> @zext4(<4 x i32> %A) nounwind {
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%B = zext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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; CHECK: zext8
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; CHECK: vpmovzxwd
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; CHECK-NOT: vinsert
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; CHECK: ret
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define <8 x i32> @zext8(<8 x i16> %A) nounwind {
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%B = zext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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; CHECK: zext_8i8_8i32
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; CHECK: vpmovzxwd
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; CHECK: vpand
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; CHECK: ret
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define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind {
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%B = zext <8 x i8> %A to <8 x i32>
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ret <8 x i32>%B
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}
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; CHECK: load_sext_test1
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; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}}
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; CHECK: ret
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define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
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%X = load <4 x i32>* %ptr
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%Y = sext <4 x i32> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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; CHECK: load_sext_test2
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; CHECK: vpmovsxbq (%r{{[^,]*}}), %ymm{{.*}}
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; CHECK: ret
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define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
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%X = load <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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; CHECK: load_sext_test3
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; CHECK: vpmovsxwq (%r{{[^,]*}}), %ymm{{.*}}
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; CHECK: ret
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define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
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%X = load <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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; CHECK: load_sext_test4
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; CHECK: vpmovsxwd (%r{{[^,]*}}), %ymm{{.*}}
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; CHECK: ret
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define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
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%X = load <8 x i16>* %ptr
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%Y = sext <8 x i16> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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; CHECK: load_sext_test5
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; CHECK: vpmovsxbd (%r{{[^,]*}}), %ymm{{.*}}
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; CHECK: ret
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define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) {
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%X = load <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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