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e89c19ab7b
This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
43 lines
915 B
LLVM
43 lines
915 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
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; rdar://5752025
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; We want:
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; CHECK: movl $42, %ecx
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; CHECK-NEXT: movl 4(%esp), %eax
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; CHECK-NEXT: andl $15, %eax
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; CHECK-NEXT: cmovnel %ecx, %eax
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; CHECK-NEXT: ret
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;
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; We don't want:
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; movl 4(%esp), %eax
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; movl %eax, %ecx # bad: extra copy
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; andl $15, %ecx
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; testl $15, %eax # bad: peep obstructed
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; movl $42, %eax
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; cmovel %ecx, %eax
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; ret
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;
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; We also don't want:
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; movl $15, %ecx # bad: larger encoding
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; andl 4(%esp), %ecx
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; movl $42, %eax
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; cmovel %ecx, %eax
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; ret
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;
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; We also don't want:
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; movl 4(%esp), %ecx
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; andl $15, %ecx
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; testl %ecx, %ecx # bad: unnecessary test
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; movl $42, %eax
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; cmovel %ecx, %eax
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; ret
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define i32 @t1(i32 %X) nounwind {
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entry:
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%tmp2 = and i32 %X, 15 ; <i32> [#uses=2]
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%tmp4 = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1]
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%retval = select i1 %tmp4, i32 %tmp2, i32 42 ; <i32> [#uses=1]
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ret i32 %retval
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}
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