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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
39 lines
1.9 KiB
LLVM
39 lines
1.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; XUN: llc -march=r600 -mcpu=rv770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: {{^}}test_umad24:
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; SI: v_mad_u32_u24
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; EG: MULADD_UINT24
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; R600: MULLO_UINT
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; R600: ADD_INT
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define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
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%mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
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store i32 %mad, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}commute_umad24:
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; SI-DAG: buffer_load_dword [[SRC0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[SRC2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI: v_mad_u32_u24 [[RESULT:v[0-9]+]], 4, [[SRC0]], [[SRC2]]
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; SI: buffer_store_dword [[RESULT]]
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define void @commute_umad24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%out.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%src0.gep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%src2.gep = getelementptr i32 addrspace(1)* %src0.gep, i32 1
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%src0 = load i32 addrspace(1)* %src0.gep, align 4
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%src2 = load i32 addrspace(1)* %src2.gep, align 4
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%mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone
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store i32 %mad, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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