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a4a46c15fe
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
llvm-svn: 206185
76 lines
2.3 KiB
LLVM
76 lines
2.3 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck -check-prefix=EL %s
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; RUN: llc -march=mips64 -mcpu=mips4 -mattr=n64 < %s | FileCheck -check-prefix=EB %s
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck -check-prefix=EL %s
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; RUN: llc -march=mips64 -mcpu=mips64 -mattr=n64 < %s | FileCheck -check-prefix=EB %s
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%struct.SLL = type { i64 }
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%struct.SI = type { i32 }
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%struct.SUI = type { i32 }
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@sll = common global %struct.SLL zeroinitializer, align 1
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@si = common global %struct.SI zeroinitializer, align 1
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@sui = common global %struct.SUI zeroinitializer, align 1
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define i64 @foo_load_ll() nounwind readonly {
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entry:
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; EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
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; EL: ldr $[[R0]], 0($[[R1]])
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; EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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; EB: ldr $[[R0]], 7($[[R1]])
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%0 = load i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1
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ret i64 %0
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}
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define i64 @foo_load_i() nounwind readonly {
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entry:
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; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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; EL: lwr $[[R0]], 0($[[R1]])
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; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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; EB: lwr $[[R0]], 3($[[R1]])
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%0 = load i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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define i64 @foo_load_ui() nounwind readonly {
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entry:
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; EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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; EL: lwr $[[R0]], 0($[[R1]])
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; EL: daddiu $[[R2:[0-9]+]], $zero, 1
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; EL: dsll $[[R3:[0-9]+]], $[[R2]], 32
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; EL: daddiu $[[R4:[0-9]+]], $[[R3]], -1
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; EL: and ${{[0-9]+}}, $[[R0]], $[[R4]]
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; EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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; EB: lwr $[[R0]], 3($[[R1]])
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%0 = load i32* getelementptr inbounds (%struct.SUI* @sui, i64 0, i32 0), align 1
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%conv = zext i32 %0 to i64
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ret i64 %conv
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}
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define void @foo_store_ll(i64 %a) nounwind {
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entry:
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; EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
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; EL: sdr $[[R0]], 0($[[R1]])
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; EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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; EB: sdr $[[R0]], 7($[[R1]])
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store i64 %a, i64* getelementptr inbounds (%struct.SLL* @sll, i64 0, i32 0), align 1
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ret void
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}
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define void @foo_store_i(i32 %a) nounwind {
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entry:
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; EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
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; EL: swr $[[R0]], 0($[[R1]])
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; EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
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; EB: swr $[[R0]], 3($[[R1]])
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store i32 %a, i32* getelementptr inbounds (%struct.SI* @si, i64 0, i32 0), align 1
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ret void
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}
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