Daniel Sanders b0144748c0 [mips] Range check vsplat_simm5 and vsplat_simm10 ... Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18177 llvm-svn: 264287		2016-03-24 14:53:40 +00:00
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AArch64	[AArch64] Replace some uses of report_fatal_error with reportError in AArch64 ELF object writer	2016-03-23 13:45:03 +00:00
AMDGPU	[AMDGPU] Fix missing assembler predicates.	2016-03-23 04:27:26 +00:00
ARM	ARM: Support relative references using the PREL31 symbol variant.	2016-03-10 19:30:18 +00:00
AsmParser	[MCParser] Accept uppercase radix variants 0X and 0B	2016-03-18 18:22:07 +00:00
COFF
Disassembler	[mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions	2016-03-24 09:22:45 +00:00
ELF	[ELF][gcc compatibility]: support section names with special characters (e.g. "/")	2016-03-22 11:23:15 +00:00
Hexagon	[Hexagon] Add handling fixups and instruction relaxation	2016-03-21 20:27:17 +00:00
MachO	[MachO] Extend the alt_entry support for aliases added in r263521 to	2016-03-15 04:20:49 +00:00
Markup
Mips	[mips] Range check vsplat_simm5 and vsplat_simm10	2016-03-24 14:53:40 +00:00
PowerPC	[Power9] Implement new vsx instructions: load, store instructions for vector and scalar	2016-03-08 03:49:13 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ
X86	[llvm-objdump] Print <unknown> in place of instruction text if it couldn't be disassembled.	2016-03-18 16:26:48 +00:00