..
GlobalISel
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend
2020-06-18 13:15:13 +01:00
ParallelDSP
Infer alignment of unmarked loads in IR/bitcode parsing.
2020-05-14 13:03:50 -07:00
Windows
2006-11-10-CycleInDAG.ll
2007-01-19-InfiniteLoop.ll
2007-03-07-CombinerCrash.ll
2007-03-13-InstrSched.ll
2007-03-21-JoinIntervalsCrash.ll
2007-03-27-RegScavengerAssert.ll
2007-03-30-RegScavengerAssert.ll
2007-04-02-RegScavengerAssert.ll
2007-04-03-PEIBug.ll
2007-04-03-UndefinedSymbol.ll
2007-04-30-CombinerCrash.ll
2007-05-03-BadPostIndexedLd.ll
2007-05-07-tailmerge-1.ll
2007-05-09-tailmerge-2.ll
2007-05-14-InlineAsmCstCrash.ll
2007-05-14-RegScavengerAssert.ll
2007-05-22-tailmerge-3.ll
2007-05-23-BadPreIndexedStore.ll
2007-08-15-ReuseBug.ll
2008-02-04-LocalRegAllocBug.ll
2008-02-29-RegAllocLocal.ll
2008-03-05-SxtInRegBug.ll
2008-03-07-RegScavengerAssert.ll
2008-04-04-ScavengerAssert.ll
2008-04-10-ScavengerAssert.ll
2008-04-11-PHIofImpDef.ll
2008-05-19-LiveIntervalsBug.ll
2008-05-19-ScavengerAssert.ll
2008-07-17-Fdiv.ll
2008-07-24-CodeGenPrepCrash.ll
2008-08-07-AsmPrintBug.ll
2008-09-17-CoalescerBug.ll
2008-11-18-ScavengerAssert.ll
2009-02-16-SpillerBug.ll
2009-02-22-SoftenFloatVaArg.ll
2009-02-27-SpillerBug.ll
2009-03-07-SpillerBug.ll
2009-03-09-AddrModeBug.ll
2009-04-06-AsmModifier.ll
2009-04-08-AggregateAddr.ll
2009-04-08-FloatUndef.ll
2009-04-08-FREM.ll
2009-04-09-RegScavengerAsm.ll
2009-05-05-DAGCombineBug.ll
2009-05-07-RegAllocLocal.ll
2009-05-11-CodePlacementCrash.ll
2009-05-18-InlineAsmMem.ll
2009-06-02-ISelCrash.ll
2009-06-04-MissingLiveIn.ll
2009-06-15-RegScavengerAssert.ll
2009-06-19-RegScavengerAssert.ll
2009-06-22-CoalescerBug.ll
2009-06-30-RegScavengerAssert2.ll
2009-06-30-RegScavengerAssert3.ll
2009-06-30-RegScavengerAssert4.ll
2009-06-30-RegScavengerAssert5.ll
2009-06-30-RegScavengerAssert.ll
2009-07-01-CommuteBug.ll
2009-07-09-asm-p-constraint.ll
2009-07-18-RewriterBug.ll
2009-07-22-ScavengerAssert.ll
2009-07-22-SchedulerAssert.ll
2009-07-29-VFP3Registers.ll
2009-08-02-RegScavengerAssert-Neon.ll
2009-08-04-RegScavengerAssert-2.ll
2009-08-04-RegScavengerAssert.ll
2009-08-15-RegScavenger-EarlyClobber.ll
2009-08-15-RegScavengerAssert.ll
2009-08-21-PostRAKill2.ll
2009-08-21-PostRAKill3.ll
2009-08-21-PostRAKill.ll
2009-08-26-ScalarToVector.ll
2009-08-27-ScalarToVector.ll
2009-08-29-ExtractEltf32.ll
2009-08-29-TooLongSplat.ll
2009-08-31-LSDA-Name.ll
2009-08-31-TwoRegShuffle.ll
2009-09-09-AllOnes.ll
2009-09-09-fpcmp-ole.ll
2009-09-10-postdec.ll
2009-09-13-InvalidSubreg.ll
2009-09-13-InvalidSuperReg.ll
2009-09-20-LiveIntervalsBug.ll
2009-09-21-LiveVariablesBug.ll
2009-09-22-LiveVariablesBug.ll
2009-09-23-LiveVariablesBug.ll
2009-09-24-spill-align.ll
2009-09-27-CoalescerBug.ll
2009-09-28-LdStOptiBug.ll
2009-10-02-NEONSubregsBug.ll
2009-10-16-Scope.ll
2009-10-27-double-align.ll
2009-10-30.ll
2009-11-01-NeonMoves.ll
2009-11-02-NegativeLane.ll
2009-11-07-SubRegAsmPrinting.ll
2009-11-13-CoalescerCrash.ll
2009-11-13-ScavengerAssert2.ll
2009-11-13-ScavengerAssert.ll
2009-11-13-VRRewriterCrash.ll
2009-11-30-LiveVariablesBug.ll
2009-12-02-vtrn-undef.ll
2010-03-04-eabi-fp-spill.ll
2010-03-04-stm-undef-addr.ll
2010-03-18-ldm-rtrn.ll
2010-04-09-NeonSelect.ll
2010-04-13-v2f64SplitArg.ll
2010-04-14-SplitVector.ll
2010-04-15-ScavengerDebugValue.ll
2010-05-14-IllegalType.ll
2010-05-17-FastAllocCrash.ll
2010-05-18-LocalAllocCrash.ll
2010-05-18-PostIndexBug.ll
2010-05-19-Shuffles.ll
2010-05-20-NEONSpillCrash.ll
2010-05-21-BuildVector.ll
2010-06-11-vmovdrr-bitcast.ll
2010-06-21-LdStMultipleBug.ll
2010-06-21-nondarwin-tc.ll
2010-06-25-Thumb2ITInvalidIterator.ll
2010-06-29-PartialRedefFastAlloc.ll
2010-06-29-SubregImpDefs.ll
2010-07-26-GlobalMerge.ll
2010-08-04-EHCrash.ll
2010-08-04-StackVariable.ll
ARM: Reduce debug info testcase
2020-06-03 10:33:32 -04:00
2010-09-21-OptCmpBug.ll
2010-10-25-ifcvt-ldm.ll
2010-11-15-SpillEarlyClobber.ll
2010-11-29-PrologueBug.ll
2010-12-07-PEIBug.ll
2010-12-08-tpsoft.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
2010-12-15-elf-lcomm.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
2010-12-17-LocalStackSlotCrash.ll
2011-01-19-MergedGlobalDbg.ll
2011-02-04-AntidepMultidef.ll
2011-02-07-AntidepClobber.ll
2011-03-10-DAGCombineCrash.ll
2011-03-15-LdStMultipleBug.ll
2011-03-23-PeepholeBug.ll
2011-04-07-schediv.ll
2011-04-11-MachineLICMBug.ll
2011-04-12-AlignBug.ll
2011-04-12-FastRegAlloc.ll
2011-04-15-AndVFlagPeepholeBug.ll
2011-04-15-RegisterCmpPeephole.ll
2011-04-26-SchedTweak.ll
2011-04-27-IfCvtBug.ll
2011-05-04-MultipleLandingPadSuccs.ll
2011-06-09-TailCallByVal.ll
2011-06-16-TailCallByVal.ll
2011-06-29-MergeGlobalsAlign.ll
2011-07-10-GlobalMergeBug.ll
2011-08-02-MergedGlobalDbg.ll
2011-08-12-vmovqqqq-pseudo.ll
2011-08-25-ldmia_ret.ll
2011-08-29-ldr_pre_imm.ll
2011-08-29-SchedCycle.ll
2011-09-09-OddVectorDivision.ll
2011-09-19-cpsr.ll
2011-09-28-CMovCombineBug.ll
2011-10-26-ExpandUnalignedLoadCrash.ll
2011-10-26-memset-inline.ll
2011-10-26-memset-with-neon.ll
2011-11-07-PromoteVectorLoadStore.ll
2011-11-09-BitcastVectorDouble.ll
2011-11-09-IllegalVectorFPIntConvert.ll
2011-11-14-EarlyClobber.ll
2011-11-28-DAGCombineBug.ll
2011-11-29-128bitArithmetics.ll
2011-11-30-MergeAlignment.ll
2011-12-14-machine-sink.ll
2011-12-19-sjlj-clobber.ll
2012-01-23-PostRA-LICM.ll
2012-01-24-RegSequenceLiveRange.ll
2012-01-26-CoalescerBug.ll
2012-01-26-CopyPropKills.ll
2012-02-01-CoalescerBug.ll
2012-03-05-FPSCR-bug.ll
2012-03-13-DAGCombineBug.ll
2012-03-26-FoldImmBug.ll
2012-04-02-TwoAddrInstrCrash.ll
2012-04-10-DAGCombine.ll
2012-04-24-SplitEHCriticalEdge.ll
2012-05-04-vmov.ll
2012-05-10-PreferVMOVtoVDUP32.ll
2012-05-29-TailDupBug.ll
2012-06-12-SchedMemLatency.ll
2012-08-04-DtripleSpillReload.ll
2012-08-08-legalize-unaligned.ll
2012-08-09-neon-extload.ll
2012-08-13-bfi.ll
2012-08-23-legalize-vmull.ll
2012-08-27-CopyPhysRegCrash.ll
2012-08-30-select.ll
2012-09-18-ARMv4ISelBug.ll
2012-09-25-InlineAsmScalarToVectorConv2.ll
2012-09-25-InlineAsmScalarToVectorConv.ll
2012-10-04-AAPCS-byval-align8.ll
2012-10-04-FixedFrame-vs-byval.ll
2012-10-04-LDRB_POST_IMM-Crash.ll
2012-10-18-PR14099-ByvalFrameAddress.ll
2012-11-14-subs_carry.ll
2013-01-21-PR14992.ll
2013-02-27-expand-vfma.ll
2013-04-05-Small-ByVal-Structs-PR15293.ll
2013-04-16-AAPCS-C4-vs-VFP.ll
2013-04-16-AAPCS-C5-vs-VFP.ll
2013-04-18-load-overlap-PR14824.ll
2013-04-21-AAPCS-VA-C.1.cp.ll
2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
2013-05-05-IfConvertBug.ll
2013-05-07-ByteLoadSameAddress.ll
2013-05-13-AAPCS-byval-padding2.ll
2013-05-13-AAPCS-byval-padding.ll
2013-05-13-DAGCombiner-undef-mask.ll
2013-05-31-char-shift-crash.ll
2013-06-03-ByVal-2Kbytes.ll
2013-07-29-vector-or-combine.ll
2013-10-11-select-stalls.ll
2013-11-08-inline-asm-neon-array.ll
2014-01-09-pseudo_expand_implicit_reg.ll
2014-02-05-vfp-regs-after-stack.ll
2014-02-21-byval-reg-split-alignment.ll
2014-05-14-DwarfEHCrash.ll
2014-07-18-earlyclobber-str-post.ll
2014-08-04-muls-it.ll
2015-01-21-thumbv4t-ldstr-opt.ll
2016-05-01-RegScavengerAssert.ll
2016-08-24-ARM-LDST-dbginfo-bug.ll
2018-02-13-PR36079.ll
a15-mla.ll
a15-partial-update.ll
a15-SD-dep.ll
a15.ll
aapcs-hfa-code.ll
aapcs-hfa.ll
acle-intrinsics-rot.ll
acle-intrinsics-v5.ll
acle-intrinsics.ll
add-like-or.ll
add-sub-imm.ll
[ARM] Optimize immediate selection
2020-07-29 13:29:17 +01:00
addrmode.ll
addrspacecast.ll
addsubcarry-promotion.ll
addsubo-legalization.ll
adv-copy-opt.ll
aeabi-read-tp.ll
aggregate-padding.ll
alias_align.ll
alias_store.ll
aliases.ll
align-sp-adjustment.ll
align.ll
alloc-no-stack-realign.ll
[SelectionDAG] Don't promote the alignment of allocas beyond the stack alignment.
2020-05-11 17:39:00 -07:00
alloca-align.ll
alloca.ll
analyze-branch-bkpt.ll
and-cmpz.ll
and-load-combine.ll
Fix invalid alignment in DAGCombiner::isLegalNarrowLdSt
2020-06-29 09:22:15 +00:00
apcs-vfp.ll
arg-copy-elide.ll
argaddr.ll
arguments2.ll
arguments3.ll
arguments4.ll
arguments5.ll
arguments6.ll
arguments7.ll
arguments8.ll
arguments_f64_backfill.ll
arguments-nosplit-double.ll
arguments-nosplit-i64.ll
arguments.ll
arm32-round-conv.ll
arm32-rounding.ll
arm-abi-attr.ll
arm-and-tst-peephole.ll
arm-asm.ll
arm-bf16-dotprod-intrinsics.ll
[ARM] BFloat MatMul Intrinsics&CodeGen
2020-06-23 12:06:37 +00:00
arm-bf16-pcs.ll
[ARM][BFloat] Legalize bf16 type even without fullfp16.
2020-06-24 09:36:26 +01:00
arm-eabi.ll
arm-frame-lowering-no-terminator.ll
arm-frameaddr.ll
arm-half-promote.ll
[NFC][test] Adding fastcc test case for promoted 16-bit integer bitcasts.
2020-07-09 11:38:49 -07:00
arm-insert-subvector.ll
arm-macho-tail.ll
arm-matmul.ll
[AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics
2020-04-24 15:54:06 +01:00
arm-modifier.ll
arm-negative-stride.ll
arm-position-independence-jump-table.ll
arm-position-independence.ll
arm-returnaddr.ll
arm-shrink-wrapping-linux.ll
arm-shrink-wrapping.ll
arm-storebytesmerge.ll
arm-ttype-target2.ll
arm-vld1.ll
arm-vlddup-update.ll
arm-vlddup.ll
arm-vst1.ll
ARMLoadStoreDBG.mir
armv4.ll
armv8.2a-fp16-vector-intrinsics.ll
atomic-64bit.ll
atomic-cmp.ll
atomic-cmpxchg.ll
atomic-load-store.ll
atomic-op.ll
atomic-ops-m33.ll
atomic-ops-v8.ll
atomicrmw_minmax.ll
available_externally.ll
avoid-cpsr-rmw.ll
bf16-convert-intrinsics.ll
[BFloat] Add convert/copy instrinsic support
2020-06-23 14:27:05 +00:00
bf16-create-get-set-dup.ll
[ARM][BFloat] Lowering of create/get/set/dup intrinsics
2020-06-19 12:52:40 +00:00
bf16-getlane-with-fp16.ll
[ARM][BFloat] Lowering of create/get/set/dup intrinsics
2020-06-19 12:52:40 +00:00
bf16-intrinsics-ld-st.ll
[ARM][BFloat] Implement lowering of bf16 load/store intrinsics
2020-06-19 14:02:35 +00:00
bfc.ll
bfi.ll
bfloat.ll
[ARM] Basic bfloat support
2020-06-18 17:26:24 +01:00
bfx.ll
bic.ll
bicZext.ll
big-endian-eh-unwind.ll
big-endian-neon-bitconv.ll
big-endian-neon-extend.ll
big-endian-neon-fp16-bitconv.ll
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
big-endian-neon-trunc-store.ll
big-endian-ret-f64.ll
big-endian-vector-callee.ll
big-endian-vector-caller.ll
big-endian-vmov.ll
bit-reverse-to-rbit.ll
bits.ll
bool-ext-inc.ll
bswap16.ll
bswap-inline-asm.ll
build-attributes-encoding.s
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
build-attributes-fn-attr0.ll
build-attributes-fn-attr1.ll
build-attributes-fn-attr2.ll
build-attributes-fn-attr3.ll
build-attributes-fn-attr4.ll
build-attributes-fn-attr5.ll
build-attributes-fn-attr6.ll
build-attributes-optimization-minsize.ll
build-attributes-optimization-mixed.ll
build-attributes-optimization-optnone.ll
build-attributes-optimization-optsize.ll
build-attributes-optimization.ll
build-attributes.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
bx_fold.ll
byval_load_align.ll
byval-align.ll
cache-intrinsic.ll
call_nolink.ll
call-noret-minsize.ll
call-noret.ll
call-tc.ll
call.ll
carry.ll
cbz-implicit-it-range.ll
cfguard-checks.ll
cfguard-module-flag.ll
cfi-alignment.ll
clang-section.ll
cls.ll
clz.ll
cmn.ll
cmov_fp16.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
cmp1-peephole-thumb.mir
cmp2-peephole-thumb.mir
cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
cmp.ll
cmpxchg-idioms.ll
cmpxchg-O0-be.ll
cmpxchg-O0.ll
cmpxchg-weak.ll
cmpxchg.mir
cmse-clear-float-bigend.mir
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-clear-float-hard2.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-clear-float-hard.ll
[ARM] Moving CMSE handling of half arguments and return to the backend
2020-06-18 13:16:29 +01:00
cmse-clear-float-mve.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-clear-float.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-clear.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-clrm-it-block.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-expand-bxns-ret.mir
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
cmse-vlldm-no-reorder.ll
[ARM] Describe defs/uses of VLLDM and VLSTM
2020-06-23 16:04:23 +01:00
cmse-vlldm-no-reorder.mir
[ARM] Describe defs/uses of VLLDM and VLSTM
2020-06-23 16:04:23 +01:00
cmse.ll
Re-commit: [ARM] CMSE code generation
2020-05-14 16:46:16 +01:00
coalesce-dbgvalue.ll
coalesce-subregs.ll
code-placement.ll
codemodel.ll
codesize-ifcvt.mir
coff-no-dead-strip.ll
combine-movc-sub.ll
combine-vmovdrr.ll
commute-movcc.ll
compare-call.ll
const-load-align-thumb.mir
[Thumb] set code alignment for 16-bit load from constant pool
2020-07-22 10:12:41 +01:00
constant-island-crash.ll
constant-island-movwt.mir
constant-islands-cfg.mir
constant-islands-split-IT.mir
constant-islands.ll
constantfp.ll
[ARM][XO] Execute-only miscompiles double literals for big-endian
2020-06-08 08:13:08 +01:00
constantpool-align.ll
constantpool-promote-dbg.ll
constantpool-promote-duplicate.ll
constantpool-promote-ldrh.ll
constantpool-promote.ll
constants.ll
copy-by-struct-i32.ll
copy-cpsr.ll
copy-paired-reg.ll
cortex-a57-misched-alu.ll
cortex-a57-misched-basic.ll
cortex-a57-misched-ldm-wrback.ll
cortex-a57-misched-ldm.ll
cortex-a57-misched-stm-wrback.ll
cortex-a57-misched-stm.ll
cortex-a57-misched-vadd.ll
cortex-a57-misched-vfma.ll
cortex-a57-misched-vldm-wrback.ll
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
cortex-a57-misched-vldm.ll
cortex-a57-misched-vstm-wrback.ll
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
cortex-a57-misched-vstm.ll
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
cortex-a57-misched-vsub.ll
cortexr52-misched-basic.ll
crash-greedy-v6.ll
crash-greedy.ll
crash-O0.ll
crash-on-pow2-shufflevector.ll
crash-shufflevector.ll
crash.ll
crc32.ll
cse-call.ll
cse-flags.ll
cse-ldrlit.ll
cse-libcalls.ll
csr-split.ll
ctor_order.ll
ctors_dtors.ll
cttz_vector.ll
cttz.ll
cxx-tlscc.ll
dag-combine-ldst.ll
dagcombine-anyexttozeroext.ll
dagcombine-concatvector.ll
darwin-eabi.ll
darwin-tls-preserved.ll
darwin-tls.ll
data-in-code-annotations.ll
dbg-range-extension.mir
dbg-tcreturn.ll
[ScheduleDAG] Move DBG_VALUEs after first term forward.
2020-07-17 10:27:43 +01:00
dbg.ll
DbgValueOtherTargets.test
debug-frame-large-stack.ll
debug-frame-no-debug.ll
debug-frame-vararg.ll
debug-frame.ll
debug-info-arg.ll
debug-info-blocks.ll
debug-info-branch-folding.ll
debug-info-d16-reg.ll
debug-info-no-frame.ll
debug-info-qreg.ll
debug-info-s16-reg.ll
debug-info-sreg2.ll
debug-segmented-stacks.ll
debuginfo-split-carryexpr.ll
debugtrap.ll
default-float-abi.ll
default-reloc.ll
demanded-bits-and.ll
deprecated-asm.s
deps-fix.ll
disable-fp-elim.ll
disable-tail-calls.ll
div.ll
divmod-eabi.ll
divmod-hwdiv.ll
divmod.ll
domain-conv-vmovs.ll
dsp-loop-indexing.ll
dsp-mlal.ll
dwarf-eh.ll
dwarf-frame.ll
dwarf-unwind.ll
dyn-stackalloc.ll
early-cfi-sections.ll
eh-dispcont.ll
eh-resume-darwin.ll
ehabi-filters.ll
ehabi-handlerdata-nounwind.ll
ehabi-handlerdata.ll
ehabi-no-landingpad.ll
ehabi-unwind.ll
ehabi.ll
elf-lcomm-align.ll
emit-big-cst.ll
[AsmPrinter] Fix emission of non-standard integer constants for BE targets
2020-04-27 14:57:29 -07:00
emutls1.ll
emutls_generic.ll
emutls.ll
execute-only-big-stack-frame.ll
execute-only-section.ll
execute-only.ll
expand-pseudos.mir
extload-knownzero.ll
extloadi1.ll
fabs-neon.ll
fabs-to-bfc.ll
fabss.ll
fadds.ll
fast-isel-align.ll
fast-isel-binary.ll
fast-isel-br-const.ll
fast-isel-br-phi.ll
fast-isel-call-multi-reg-return.ll
fast-isel-call.ll
fast-isel-cmp-imm.ll
fast-isel-conversion.ll
fast-isel-crash2.ll
fast-isel-crash.ll
fast-isel-deadcode.ll
fast-isel-ext.ll
fast-isel-fold.ll
fast-isel-frameaddr.ll
fast-isel-GEP-coalesce.ll
fast-isel-icmp.ll
fast-isel-indirectbr.ll
fast-isel-inline-asm.ll
fast-isel-intrinsic.ll
fast-isel-ldr-str-arm.ll
fast-isel-ldr-str-thumb-neg-index.ll
fast-isel-ldrh-strh-arm.ll
fast-isel-load-store-verify.ll
fast-isel-mvn.ll
fast-isel-pic.ll
fast-isel-pie.ll
fast-isel-pred.ll
fast-isel-redefinition.ll
fast-isel-remat-same-constant.ll
fast-isel-ret.ll
fast-isel-select.ll
fast-isel-shift-materialize.ll
fast-isel-shifter.ll
fast-isel-static.ll
fast-isel-update-valuemap-for-extract.ll
fast-isel-vaddd.ll
fast-isel-vararg.ll
fast-isel.ll
fast-tail-call.ll
fastcc-vfp.ll
fastisel-gep-promote-before-add.ll
fastisel-thumb-litpool.ll
favor-low-reg-for-Osize.ll
fcmp-xo.ll
fcopysign.ll
[ARM] VBIT/VBIF support added.
2020-07-16 11:25:53 +01:00
fdivs.ll
fence-singlethread.ll
fixunsdfdi.ll
flag-crash.ll
float-helpers.s
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
floorf.ll
fmacs.ll
fmdrr-fmrrd.ll
fmscs.ll
fmuls.ll
fnattr-trap.ll
fnegs.ll
fnmacs.ll
fnmscs.ll
fnmul.ll
fnmuls.ll
fold-const.ll
fold-sext-sextload.ll
[ARM] Mark some tests as not safe for -debugify-and-strip-all, NFC
2020-04-22 17:03:39 -07:00
fold-stack-adjust.ll
fold-zext-zextload.ll
[ARM] Mark some tests as not safe for -debugify-and-strip-all, NFC
2020-04-22 17:03:39 -07:00
formal.ll
fp16-args.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
fp16-bitcast.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
fp16-frame-lowering.ll
fp16-fullfp16.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
fp16-fusedMAC.ll
fp16-insert-extract.ll
[ARM] VCVTT fpround instruction selection
2020-06-26 10:24:06 +01:00
fp16-instructions.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
fp16-intrinsic-vector-1op.ll
fp16-intrinsic-vector-2op.ll
fp16-litpool2-arm.mir
fp16-litpool3-arm.mir
fp16-litpool-arm.mir
fp16-litpool-thumb.mir
fp16-load-store.ll
fp16-no-condition.ll
fp16-promote.ll
[ARM] VBIT/VBIF support added.
2020-07-16 11:25:53 +01:00
fp16-v3.ll
fp16-vector-argument.ll
fp16-vld.ll
fp16-vldlane-vstlane.ll
fp16-vminmaxnm-safe.ll
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend
2020-06-18 13:15:13 +01:00
fp16-vminmaxnm-vector.ll
fp16-vminmaxnm.ll
fp16.ll
fp_convert.ll
fp-arg-shuffle.ll
fp-fast.ll
fp-intrinsics.ll
fp-only-sp.ll
fp.ll
fparith.ll
fpcmp_ueq.ll
fpcmp-f64-neon-opt.ll
fpcmp-opt.ll
fpcmp.ll
fpconsts.ll
fpconv.ll
fpmem.ll
fpoffset_overflow.mir
fpow.ll
fpowi.ll
fpscr-intrinsics.ll
fptoint.ll
fpvcvtr.ll
fragmented-args-multiple-regs.ll
frame-register.ll
freeze-soften.ll
fsubs.ll
ftrunc.ll
func-argpassing-endian.ll
fusedMAC.ll
gep-optimization.ll
ghc-tcreturn-lowered.ll
global-merge-1.ll
global-merge-addrspace.ll
global-merge-alignment.ll
global-merge-dllexport.ll
global-merge-external-2.ll
global-merge-external.ll
global-merge.ll
globals.ll
gnu_mcount_nc.ll
gpr-paired-spill-thumbinst.ll
gpr-paired-spill.ll
gv-stubs-crash.ll
half.ll
hardfloat_neon.ll
hello.ll
hfa-in-contiguous-registers.ll
hidden-vis-2.ll
hidden-vis-3.ll
hidden-vis.ll
hints.ll
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
i1.ll
i64_volatile_load_store.ll
[ARM] Improve codegen of volatile load/store of i64
2020-05-28 10:52:43 +01:00
iabs.ll
ifconv-kills.ll
ifconv-regmask.ll
ifcvt1.ll
ifcvt2.ll
ifcvt3.ll
Correctly modify the CFG in IfConverter, and then remove the
2020-05-07 18:17:07 -04:00
ifcvt4.ll
ifcvt5.ll
ifcvt6.ll
ifcvt7.ll
ifcvt8.ll
ifcvt9.ll
ifcvt10.ll
ifcvt11.ll
ifcvt12.ll
ifcvt_canFallThroughTo.mir
ifcvt_diamond_unanalyzable.mir
ifcvt_diamondSameTrueFalse.mir
ifcvt_forked_diamond_unanalyzable.mir
ifcvt_simple_bad_zero_prob_succ.mir
ifcvt_simple_unanalyzable.mir
ifcvt_triangleSameCvtNext.mir
ifcvt_triangleWoCvtToNextEdge.mir
ifcvt-branch-weight-bug.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
ifcvt-branch-weight.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
ifcvt-callback.ll
ifcvt-dead-def.ll
ifcvt-diamond-unanalyzable-common.mir
Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.
2020-07-01 12:51:50 -04:00
ifcvt-iter-indbr.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
ifcvt-regmask-noreturn.ll
ifcvt-size.mir
Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.
2020-07-01 12:51:50 -04:00
illegal-bitfield-loadstore.ll
illegal-vector-bitcast.ll
imm-peephole-arm.mir
imm-peephole-thumb.mir
imm.ll
immcost.ll
inc-of-add.ll
indexed-mem.ll
indirect-hidden.ll
indirect-reg-input.ll
indirectbr-2.ll
indirectbr-3.ll
indirectbr.ll
inline-asm-clobber.ll
inline-asm-i-constraint-i1.ll
inline-asm-multilevel-gep.ll
inline-asm-reserved-registers.ll
inline-diagnostics.ll
inlineasm2.ll
inlineasm3.ll
inlineasm4.ll
inlineasm-64bit.ll
inlineasm-error-t-toofewregs.ll
inlineasm-global.ll
inlineasm-imm-arm.ll
inlineasm-imm-thumb2.ll
inlineasm-imm-thumb.ll
inlineasm-ldr-pseudo.ll
inlineasm-operand-implicit-cast.ll
inlineasm-output-template.ll
inlineasm-switch-mode-oneway-from-arm.ll
inlineasm-switch-mode-oneway-from-thumb.ll
inlineasm-switch-mode.ll
inlineasm-X-allocation.ll
inlineasm-X-constraint.ll
inlineasm.ll
insn-sched1.ll
int-to-fp.ll
integer_insertelement.ll
interrupt-attr.ll
interval-update-remat.ll
interwork.ll
intrinsics-cmse.ll
intrinsics-coprocessor.ll
intrinsics-crypto.ll
intrinsics-memory-barrier.ll
intrinsics-overflow.ll
intrinsics-v8.ll
invalid-target.ll
invalidated-save-point.ll
invoke-donothing-assert.ll
ipra-exact-definition.ll
ipra-no-csr.ll
ipra-r0-returned.ll
ipra-reg-usage.ll
ipra.ll
isel-v8i32-crash.ll
ispositive.ll
jump-table-islands-split.ll
jump-table-islands.ll
jump-table-tbh.ll
jumptable-label.ll
krait-cpu-div-attribute.ll
large-stack.ll
large-vector.ll
ldaex-stlex.ll
ldc2l.ll
ldm-base-writeback.ll
ldm-stm-base-materialization.ll
ldm-stm-i256.ll
ldm.ll
ldr_ext.ll
ldr_frame.ll
ldr_post.ll
ldr_pre.ll
ldr.ll
ldrcppic.ll
ldrd-memoper.ll
ldrd.ll
ldrex-frame-size.ll
ldst-f32-2-i32.ll
ldstrex-m.ll
ldstrex.ll
legalize-bitcast.ll
RegAllocFast: Record internal state based on register units
2020-06-03 16:51:46 -04:00
legalize-fneg.ll
legalize-unaligned-load.ll
lit.local.cfg
litpool-licm.ll
llrint-conv.ll
llround-conv.ll
load_i1_select.ll
load_store_multiple.ll
load_store_opt_clobber_cpsr.mir
load_store_opt_kill.mir
load_store_opt_reg_limit.mir
load-address-masked.ll
load-arm.ll
load-combine-big-endian.ll
load-combine.ll
load-global2.ll
load-global.ll
load-store-flags.ll
load.ll
local-call.ll
log2_not_readnone.ll
long_shift.ll
long-setcc.ll
long.ll
longMAC.ll
loop-align-cortex-m.ll
loop-indexing.ll
loopvectorize_pr33804.ll
lower-vmax.ll
lowerMUL-newload.ll
lrint-conv.ll
lround-conv.ll
lsr-code-insertion.ll
lsr-icmp-imm.ll
lsr-scale-addr-mode.ll
lsr-setupcost.ll
lsr-undef-in-binop.ll
lsr-unfolded-offset.ll
machine-copyprop.mir
machine-cse-cmp.ll
machine-licm.ll
machine-outliner-lr-regsave.mir
[ARM][MachineOutliner] Add LR RegSave mode.
2020-06-15 15:22:08 +02:00
machine-outliner-no-lr-save.mir
[ARM][MachineOutliner] Fix no-lr-save testcase.
2020-06-15 16:09:31 +02:00
machine-outliner-tail.ll
[ARM][MachineOutliner] Add Machine Outliner support for ARM.
2020-05-15 08:44:23 +02:00
machine-outliner-thunk.ll
[ARM][MachineOutliner] Add Machine Outliner support for ARM.
2020-05-15 08:44:23 +02:00
machine-outliner-unoutlinable.mir
[ARM][MachineOutliner] Add Machine Outliner support for ARM.
2020-05-15 08:44:23 +02:00
machine-outliner-unsafe-registers.mir
[ARM][MachineOutliner] Add Machine Outliner support for ARM.
2020-05-15 08:44:23 +02:00
machine-sink-multidef.ll
machine-sink-multidef.mir
machine-verifier.mir
macho-embedded-float.ll
macho-extern-hidden.ll
macho-frame-offset.ll
MachO-subtypes.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
macho-trap.ll
mature-mc-support.ll
mcp-dest-regs-no-dup.mir
[MachineCopyPropagation] BackwardPropagatableCopy: add check for hasOverlappingMultipleDef
2020-07-29 16:21:01 +01:00
mem.ll
memcpy-inline.ll
memcpy-ldm-stm.ll
memcpy-no-inline.ll
memfunc.ll
memset-align.ll
memset-inline.ll
MergeConsecutiveStores.ll
metadata-default.ll
metadata-short-enums.ll
metadata-short-wchar.ll
minmax.ll
minsize-call-cse.ll
minsize-imms.ll
minsize-litpools.ll
misched-copy-arm.ll
misched-fp-basic.ll
misched-fusion-aes.ll
misched-fusion-lit.ll
misched-int-basic-thumb2.mir
misched-int-basic.mir
mls.ll
movcc-double.ll
movt-movw-global.ll
movt.ll
msr-it-block.ll
mul_const.ll
mul.ll
mulhi.ll
mult-alt-generic-arm.ll
mvn.ll
naked-no-prolog.ll
[ARM] prologue instructions emitted for naked function with >64 byte argument
2020-06-09 11:33:03 +01:00
named-reg-alloc.ll
named-reg-notareg.ll
negate-i1.ll
negative-offset.ll
neon_arith1.ll
neon_cmp.ll
neon_div.ll
neon_fpconv.ll
neon_ld1.ll
neon_ld2.ll
neon_minmax.ll
neon_shift.ll
neon_spill.ll
neon_vabs.ll
neon_vshl_minint.ll
neon-dot-product.ll
neon-fma.ll
neon-spfp.ll
neon-v8.1a.ll
neon-vcadd.ll
neon-vmovn.ll
neon-vqaddsub-upgrade.ll
nest-register.ll
nnan-fsub.ll
no_redundant_trunc_for_cmp.ll
no-arm-mode.ll
no-cfi.ll
no-cmov2bfi.ll
no-fpscr-liveness.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
no-fpu.ll
no-register-coalescing-in-returnsTwice.mir
Prevent register coalescing in functions whith setjmp
2020-05-16 00:36:34 +01:00
no-tail-call.ll
nomerge.ll
Add NoMerge MIFlag to avoid MIR branch folding
2020-05-29 12:31:06 -07:00
none-macho-v4t.ll
none-macho.ll
nonreserved-callframe-with-basereg.mir
noopt-dmb-v7.ll
nop_concat_vectors.ll
noreturn-csr-skip.mir
noreturn.ll
null-streamer.ll
O3-pipeline.ll
[TargetPassConfig] Add CanonicalizeFreezeInLoops before LSR
2020-05-28 05:21:12 +09:00
opt-shuff-tstore.ll
optimize-dmbs-v7.ll
optselect-regclass.ll
out-of-registers.ll
overflow-intrinsic-optimizations.ll
pack.ll
peephole-bitcast.ll
peephole-phi.mir
pei-swiftself.mir
phi.ll
pic.ll
pie.ll
plt-relative-reloc.ll
popcnt.ll
postrasched.ll
pow.75.ll
pow.ll
pr3502.ll
pr13249.ll
pr18364-movw.ll
pr25317.ll
pr25838.ll
pr26669.ll
pr32545.ll
pr32578.ll
pr34045-2.ll
pr34045.ll
pr35103.ll
pr36577.ll
pr39060.ll
pr39571.ll
pr42062.ll
pr42638-VMOVRRDCombine.ll
PR15053.ll
PR32721_ifcvt_triangle_unanalyzable.mir
PR35379.ll
preferred-align.ll
prefetch.ll
prera-ldst-aliasing.mir
prera-ldst-insertpt.mir
print-memb-operand.ll
print-registers.ll
private.ll
proc-resource-sched.ll
qdadd.ll
rbit.ll
readcyclecounter.ll
readonly-aliases.ll
readtp.ll
reg_sequence.ll
regcoal-invalid-subrange-update.mir
register-scavenger-exceptions.mir
regpair_hint_phys.ll
relax-per-target-feature.ll
rem_crash.ll
ret0.ll
ret_arg1.ll
ret_arg2.ll
ret_arg3.ll
ret_arg4.ll
ret_arg5.ll
ret_f32_arg2.ll
ret_f32_arg5.ll
ret_f64_arg2.ll
ret_f64_arg_reg_split.ll
ret_f64_arg_split.ll
ret_f64_arg_stack.ll
ret_i64_arg2.ll
ret_i64_arg3.ll
ret_i64_arg_split.ll
ret_i128_arg2.ll
ret_sret_vector.ll
ret_void.ll
returned-ext.ll
returned-trunc-tail-calls.ll
rev.ll
ror.ll
rotate.ll
sadd_sat_plus.ll
sadd_sat.ll
[ARM] Only produce qadd8b under hasV6Ops
2020-04-27 10:13:29 +01:00
sat-to-bitop.ll
saxpy10-a9.ll
sbfx.ll
sched-it-debug-nodes.mir
sdiv-pow2-arm-size.ll
sdiv-pow2-thumb-size.ll
section-name.ll
section.ll
segmented-stacks-dynamic.ll
segmented-stacks.ll
select_const.ll
select_xform.ll
select-imm.ll
[ARM] Optimize immediate selection
2020-07-29 13:29:17 +01:00
select-undef.ll
select.ll
setcc-logic.ll
setcc-type-mismatch.ll
setjmp_longjmp.ll
shift_minsize.ll
Revert "[arm][darwin] Don't generate libcalls for wide shifts on Darwin"
2020-06-08 16:37:29 -07:00
shift-combine.ll
shift-i64.ll
shifter_operand.ll
shuffle.ll
signext-inreg.ll
sincos.ll
single-issue-r52.mir
sjlj-prepare-critical-edge.ll
sjljeh-swifterror.ll
sjljehprepare-lower-empty-struct.ll
smml.ll
smul.ll
softfp-constant-comparison.ll
softfp-fabs-fneg.ll
space-directive.ll
special-reg-acore.ll
special-reg-mcore.ll
special-reg-v8m-base.ll
special-reg-v8m-main.ll
special-reg.ll
spill-q.ll
splitkit.ll
ssat-lower.ll
ssat-upper.ll
ssat-v4t.ll
ssat-with-shift.ll
[ARM] Generated SSAT and USAT instructions with shift
2020-08-04 09:38:17 +00:00
ssat.ll
ssp-data-layout.ll
ssub_sat_plus.ll
ssub_sat.ll
stack_guard_remat.ll
stack-alignment.ll
stack-frame.ll
stack-guard-reassign.ll
stack-protector-bmovpcb_call.ll
stack-size-section.ll
stackpointer.ll
static-addr-hoisting.ll
stc2.ll
stm.ll
store_half.ll
[ARM] halfword store hits llvm_unreachable with big-endian
2020-07-17 08:56:44 +01:00
str_post.ll
str_pre-2.ll
str_pre.ll
str_trunc.ll
struct_byval_arm_t1_t2.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
struct_byval.ll
struct-byval-frame-index.ll
sub-cmp-peephole.ll
sub-from-const-hoisting.ll
sub-of-not.ll
sub.ll
subreg-remat.ll
subtarget-features-long-calls.ll
subtarget-no-movt.ll
swift-atomics.ll
swift-ios.ll
swift-return.ll
swift-vldm.ll
swifterror.ll
swiftself.ll
switch-minsize.ll
sxt_rot.ll
t2-imm.ll
t2-shrink-ldrpost.ll
[ARM] Rearrange SizeReduction when using -Oz
2020-07-02 09:19:38 +01:00
t2abs-killflags.ll
tail-call-builtin.ll
tail-call-float.ll
tail-call-results.ll
[ARM] Fix tail call validity checking for varargs calls.
2020-05-04 12:34:14 -07:00
tail-call-scheduling.ll
tail-call-weak.ll
tail-call.ll
tail-dup-bundle.mir
tail-dup-kill-flags.ll
tail-dup.ll
tail-merge-branch-weight.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
tail-opts.ll
tailcall-mem-intrinsics.ll
taildup-branch-weight.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
test-sharedidx.ll
this-return.ll
thread_pointer.ll
thumb1_return_sequence.ll
thumb1-div.ll
thumb1-ldst-opt.ll
thumb1-varalloc.ll
thumb2-it-block.ll
ARM: make Thumb1 instructions non-flag-setting in IT block.
2020-07-28 13:31:17 +01:00
thumb2-size-opt.ll
thumb2-size-reduction-internal-flags.ll
thumb_indirect_calls.ll
thumb-alignment.ll
thumb-big-stack.ll
thumb-litpool.ll
thumb-stub.ll
tls1.ll
tls2.ll
tls3.ll
tls-models.ll
trap-unreachable.ll
trap.ll
trunc_ldr.ll
truncstore-dag-combine.ll
tst_teq.ll
tst-peephole.mir
twoaddrinstr.ll
uadd_sat_plus.ll
uadd_sat.ll
uint64tof64.ll
umulo-32.ll
umulo-64-legalisation-lowering.ll
umulo-128-legalisation-lowering.ll
unaligned_load_store_vector.ll
unaligned_load_store_vfp.ll
unaligned_load_store.ll
undef-sext.ll
undefined.ll
unfold-shifts.ll
unord.ll
unschedule-first-call.ll
unwind-fp.ll
unwind-init.ll
urem-opt-size.ll
usat-lower.ll
usat-upper.ll
usat-v4t.ll
usat-with-shift.ll
[ARM] Generated SSAT and USAT instructions with shift
2020-08-04 09:38:17 +00:00
usat.ll
useaa.ll
usub_sat_plus.ll
usub_sat.ll
uxt_rot.ll
uxtb.ll
v1-constant-fold.ll
v6-jumptable-clobber.mir
v6m-smul-with-overflow.ll
v6m-umul-with-overflow.ll
v7k-abi-align.ll
v7k-libcalls.ll
v7k-sincos.ll
v8m-tail-call.ll
v8m.base-jumptable_alignment.ll
va_arg.ll
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))
2020-06-12 13:53:08 -04:00
vaba.ll
vabd.ll
vabs.ll
vadd.ll
vararg_no_start.ll
varargs-spill-stack-align-nacl.ll
vargs_align.ll
vargs.ll
vbits.ll
vbsl-constant.ll
[ARM] VBIT/VBIF support added.
2020-07-16 11:25:53 +01:00
vbsl.ll
[ARM] VBIT/VBIF support added.
2020-07-16 11:25:53 +01:00
vceq.ll
vcge.ll
vcgt.ll
vcnt.ll
vcombine.ll
vcvt_combine.ll
vcvt-cost.ll
vcvt-v8.ll
vcvt.ll
[ARM] Remove hasSideEffects from FP converts
2020-07-05 16:23:24 +01:00
vdiv_combine.ll
vdup.ll
vecreduce-fadd-legalization-soft-float.ll
vecreduce-fadd-legalization-strict.ll
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend
2020-06-18 13:15:13 +01:00
vecreduce-fmul-legalization-strict.ll
[ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend
2020-06-18 13:15:13 +01:00
vector-DAGCombine.ll
vector-extend-narrow.ll
vector-load.ll
vector-promotion.ll
vector-spilling.ll
vector-store.ll
vext.ll
vfcmp.ll
vfloatintrinsics.ll
vfp-libcalls.ll
vfp-reg-stride.ll
vfp-regs-dwarf.ll
vfp.ll
vget_lane.ll
vhadd.ll
vhsub.ll
vicmp-64.ll
vicmp.ll
virtregrewriter-subregliveness.mir
vld1.ll
vld2.ll
vld3.ll
vld4.ll
vld-vst-upgrade.ll
vlddup.ll
vldlane.ll
vldm-liveness.ll
vldm-liveness.mir
vldm-sched-a9.ll
vldmia-sched.mir
vlldm-vlstm-uops.mir
[ARM] Describe defs/uses of VLLDM and VLSTM
2020-06-23 16:04:23 +01:00
vminmax.ll
vminmaxnm-safe.ll
vminmaxnm.ll
vmla.ll
vmls.ll
vmov.ll
vmul.ll
vneg.ll
vpadal.ll
vpadd.ll
vpminmax.ll
vqadd.ll
vqdmul.ll
vqshl.ll
vqshrn.ll
vqsub.ll
vrec.ll
vrev.ll
vrint.ll
vsel-fp16.ll
vsel.ll
vselect_imax.ll
[ARM] VBIT/VBIF support added.
2020-07-16 11:25:53 +01:00
vshift.ll
vshiftins.ll
vshl.ll
vshll.ll
vshrn.ll
vsra.ll
vst1.ll
vst2.ll
vst3.ll
vst4.ll
vstlane.ll
vsub.ll
vtbl.ll
vtrn.ll
vuzp.ll
vzip.ll
warn-stack.ll
weak2.ll
weak.ll
wide-compares.ll
widen-vmovs.ll
wrong-t2stmia-size-opt.ll
xray-armv6-attribute-instrumentation.ll
xray-armv7-attribute-instrumentation.ll
xray-tail-call-sled.ll
[XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)
2020-04-24 08:35:43 -07:00
zero-cycle-zero.ll
zext-logic-shift-load.ll
zextload_demandedbits.ll
