mirror of
https://github.com/RPCS3/llvm-mirror.git
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bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
176 lines
5.6 KiB
YAML
176 lines
5.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
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---
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# This should trigger an emergency spill in the register scavenger because the
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# frame offset into the large argument is too large.
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name: func0
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true,
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isAliased: false }
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- { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false,
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isAliased: false }
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body: |
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bb.0:
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; CHECK-LABEL: name: func0
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -36
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -40
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -44
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -48
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; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 52
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
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; CHECK: $r0 = t2ADDri killed $sp, 4096, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $sp = t2LDRi12 killed $r0, 40, 14 /* CC::al */, $noreg :: (load 4)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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$sp = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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---
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# This should not trigger an emergency spill yet.
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name: func1
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true,
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isAliased: false }
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- { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false,
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isAliased: false }
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body: |
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bb.0:
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; CHECK-LABEL: name: func1
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; CHECK: liveins: $r4, $r5, $r6, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -36
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -40
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -44
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; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 48
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: $r11 = t2LDRi12 $sp, 4092, 14 /* CC::al */, $noreg :: (load 4)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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$r11 = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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