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f1ff8145c5
Change to expand all arguments and return values to i64 to follow ABI. Update regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D84581
193 lines
4.9 KiB
LLVM
193 lines
4.9 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define signext i8 @func1(i8 signext %0, i8 signext %1) {
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; CHECK-LABEL: func1:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = sext i8 %0 to i32
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%4 = sext i8 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i8
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ret i8 %6
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}
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define signext i16 @func2(i16 signext %0, i16 signext %1) {
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; CHECK-LABEL: func2:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = sext i16 %0 to i32
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%4 = sext i16 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i16
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ret i16 %6
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}
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define i32 @func3(i32 %0, i32 %1) {
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; CHECK-LABEL: func3:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i32 %0, %1
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ret i32 %3
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}
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define i64 @func4(i64 %0, i64 %1) {
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; CHECK-LABEL: func4:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: sll %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i64 %0, %1
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ret i64 %3
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}
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define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
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; CHECK-LABEL: func6:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = zext i8 %0 to i32
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%4 = zext i8 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i8
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ret i8 %6
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}
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define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
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; CHECK-LABEL: func7:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (48)0
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = zext i16 %0 to i32
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%4 = zext i16 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i16
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ret i16 %6
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}
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define i32 @func8(i32 %0, i32 %1) {
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; CHECK-LABEL: func8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i32 %0, %1
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ret i32 %3
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}
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define i64 @func9(i64 %0, i64 %1) {
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; CHECK-LABEL: func9:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
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; CHECK-NEXT: sll %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i64 %0, %1
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ret i64 %3
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}
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define signext i8 @func11(i8 signext %0) {
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; CHECK-LABEL: func11:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i8 %0, 5
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ret i8 %2
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}
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define signext i16 @func12(i16 signext %0) {
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; CHECK-LABEL: func12:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i16 %0, 5
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ret i16 %2
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}
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define i32 @func13(i32 %0) {
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; CHECK-LABEL: func13:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i32 %0, 5
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ret i32 %2
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}
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define i64 @func14(i64 %0) {
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; CHECK-LABEL: func14:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sll %s0, %s0, 5
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i64 %0, 5
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ret i64 %2
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}
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define zeroext i8 @func16(i8 zeroext %0) {
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; CHECK-LABEL: func16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: lea %s1, 224
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i8 %0, 5
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ret i8 %2
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}
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define zeroext i16 @func17(i16 zeroext %0) {
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; CHECK-LABEL: func17:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: lea %s1, 65504
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i16 %0, 5
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ret i16 %2
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}
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define i32 @func18(i32 %0) {
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; CHECK-LABEL: func18:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: sla.w.sx %s0, %s0, 5
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i32 %0, 5
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ret i32 %2
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}
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define i64 @func19(i64 %0) {
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; CHECK-LABEL: func19:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sll %s0, %s0, 5
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i64 %0, 5
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ret i64 %2
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}
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