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https://github.com/RPCS3/llvm-mirror.git
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50f1e24f05
Summary: Modify lea/load/store instructions to accept `disp(index, base)` style addressing mode (called ASX format). Also, uniform the number of DAG nodes to have 3 operands for this ASX format instructions, and update selectADDR functions to lower appropriate MI. Reviewers: arsenm, simoll, k-ishizaka Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D76822
154 lines
4.4 KiB
LLVM
154 lines
4.4 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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@vi8 = common dso_local local_unnamed_addr global i8 0, align 8
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@vi16 = common dso_local local_unnamed_addr global i16 0, align 8
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@vi32 = common dso_local local_unnamed_addr global i32 0, align 8
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@vi64 = common dso_local local_unnamed_addr global i64 0, align 8
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@vf32 = common dso_local local_unnamed_addr global float 0.000000e+00, align 8
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@vf64 = common dso_local local_unnamed_addr global double 0.000000e+00, align 8
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; Function Attrs: norecurse nounwind readonly
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define void @storef64stk(double %0) {
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; CHECK-LABEL: storef64stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca double, align 8
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store double %0, double* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storef32stk(float %0) {
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; CHECK-LABEL: storef32stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: stu %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca float, align 8
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store float %0, float* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei64stk(i64 %0) {
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; CHECK-LABEL: storei64stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca i64, align 8
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store i64 %0, i64* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei32stk(i32 %0) {
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; CHECK-LABEL: storei32stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: stl %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca i32, align 8
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store i32 %0, i32* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei16stk(i16 %0) {
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; CHECK-LABEL: storei16stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st2b %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca i16, align 8
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store i16 %0, i16* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei8stk(i8 %0) {
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; CHECK-LABEL: storei8stk:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: st1b %s0, 184(, %s11)
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; CHECK-NEXT: or %s11, 0, %s9
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%addr = alloca i8, align 8
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store i8 %0, i8* %addr, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storef64com(double %0) {
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; CHECK-LABEL: storef64com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vf64@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
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; CHECK-NEXT: st %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store double %0, double* @vf64, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storef32com(float %0) {
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; CHECK-LABEL: storef32com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vf32@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
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; CHECK-NEXT: stu %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store float %0, float* @vf32, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei64com(i64 %0) {
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; CHECK-LABEL: storei64com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vi64@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
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; CHECK-NEXT: st %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store i64 %0, i64* @vi64, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei32com(i32 %0) {
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; CHECK-LABEL: storei32com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vi32@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
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; CHECK-NEXT: stl %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store i32 %0, i32* @vi32, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei16com(i16 %0) {
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; CHECK-LABEL: storei16com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vi16@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
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; CHECK-NEXT: st2b %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store i16 %0, i16* @vi16, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind readonly
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define void @storei8com(i8 %0) {
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; CHECK-LABEL: storei8com:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, vi8@lo
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
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; CHECK-NEXT: st1b %s0, (, %s1)
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; CHECK-NEXT: or %s11, 0, %s9
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store i8 %0, i8* @vi8, align 8
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ret void
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}
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