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d094523cbe
We now only add +64bit to the CPU string for "generic" CPU. All other CPU names are assumed to have the feature flag already set if they support 64-bit. I've remove the implies from CMPXCHG8 so that Feature64Bit only comes in via CPUs or user passing -mattr=+64bit. I've changed the assert to a report_fatal_error so it's not lost in Release builds. The test updates are to fix things that tripped the new error. Differential Revision: https://reviews.llvm.org/D51231 llvm-svn: 341022
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=nocona | FileCheck %s --check-prefix=PRESCOTT
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=nehalem | FileCheck %s --check-prefix=NEHALEM
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;;; TODO: (1) Some of the loads and stores are certainly unaligned and (2) the first load and first
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;;; store overlap with the second load and second store respectively.
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;;;
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;;; Is either of these sequences ideal?
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define float @foo(i8* nocapture %buf, float %a, float %b) nounwind uwtable {
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; PRESCOTT-LABEL: foo:
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; PRESCOTT: # %bb.0: # %entry
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; PRESCOTT-NEXT: movq .Ltmp0+14(%rip), %rax
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; PRESCOTT-NEXT: movq %rax, 14(%rdi)
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; PRESCOTT-NEXT: movq .Ltmp0+8(%rip), %rax
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; PRESCOTT-NEXT: movq %rax, 8(%rdi)
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; PRESCOTT-NEXT: movq .Ltmp0(%rip), %rax
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; PRESCOTT-NEXT: movq %rax, (%rdi)
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;
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; NEHALEM-LABEL: foo:
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; NEHALEM: # %bb.0: # %entry
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; NEHALEM-NEXT: movq .Ltmp0+14(%rip), %rax
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; NEHALEM-NEXT: movq %rax, 14(%rdi)
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; NEHALEM-NEXT: movups .Ltmp0(%rip), %xmm2
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; NEHALEM-NEXT: movups %xmm2, (%rdi)
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entry:
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %buf, i8* blockaddress(@foo, %out), i64 22, i1 false)
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br label %out
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out: ; preds = %entry
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%add = fadd float %a, %b
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ret float %add
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
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