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https://github.com/RPCS3/llvm-mirror.git
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1f827bf828
Followup to D75114, this patch reuses the existing MatchRotate ROTL/ROTR rotation pattern code to also recognize the more general FSHL/FSHR funnel shift patterns when we have variable shift amounts, matched with MatchFunnelPosNeg which acts in an (almost) equivalent manner to MatchRotatePosNeg.
134 lines
3.7 KiB
LLVM
134 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
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; SHLD/SHRD manual shifts
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define i64 @test1(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shldq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%and = and i64 %bits, 63
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%and64 = sub i64 64, %and
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%sh_lo = lshr i64 %lo, %and64
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%sh_hi = shl i64 %hi, %and
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test2(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shrdq %cl, %rdi, %rax
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; CHECK-NEXT: retq
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%and = and i64 %bits, 63
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%and64 = sub i64 64, %and
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%sh_lo = shl i64 %hi, %and64
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%sh_hi = lshr i64 %lo, %and
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test3(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shldq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%bits64 = sub i64 64, %bits
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%sh_lo = lshr i64 %lo, %bits64
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%sh_hi = shl i64 %hi, %bits
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test4(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shrdq %cl, %rdi, %rax
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; CHECK-NEXT: retq
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%bits64 = sub i64 64, %bits
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%sh_lo = shl i64 %hi, %bits64
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%sh_hi = lshr i64 %lo, %bits
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test5(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shldq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%bits64 = xor i64 %bits, 63
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%lo2 = lshr i64 %lo, 1
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%sh_lo = lshr i64 %lo2, %bits64
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%sh_hi = shl i64 %hi, %bits
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test6(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shrdq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%bits64 = xor i64 %bits, 63
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%lo2 = shl i64 %lo, 1
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%sh_lo = shl i64 %lo2, %bits64
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%sh_hi = lshr i64 %hi, %bits
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test7(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shrdq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%bits64 = xor i64 %bits, 63
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%lo2 = add i64 %lo, %lo
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%sh_lo = shl i64 %lo2, %bits64
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%sh_hi = lshr i64 %hi, %bits
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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define i64 @test8(i64 %hi, i64 %lo, i64 %bits) nounwind {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdx, %rcx
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
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; CHECK-NEXT: shldq %cl, %rsi, %rax
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; CHECK-NEXT: retq
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%tbits = trunc i64 %bits to i8
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%tand = and i8 %tbits, 63
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%tand64 = sub i8 64, %tand
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%and = zext i8 %tand to i64
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%and64 = zext i8 %tand64 to i64
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%sh_lo = lshr i64 %lo, %and64
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%sh_hi = shl i64 %hi, %and
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%sh = or i64 %sh_lo, %sh_hi
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ret i64 %sh
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}
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