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bbccd10c81
This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
37 lines
1.3 KiB
ArmAsm
37 lines
1.3 KiB
ArmAsm
// RUN: not llvm-mc -triple arm -mattr=+dotprod -show-encoding < %s 2> %t
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// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
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// RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t
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// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
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// Only indices 0 an 1 should be accepted:
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vudot.u8 d0, d1, d2[2]
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vsdot.s8 d0, d1, d2[2]
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vudot.u8 q0, q1, d4[2]
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vsdot.s8 q0, q1, d4[2]
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: vudot.u8 d0, d1, d2[2]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: vsdot.s8 d0, d1, d2[2]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: vudot.u8 q0, q1, d4[2]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: vsdot.s8 q0, q1, d4[2]
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// CHECK-ERROR: ^
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// Only the lower 16 D-registers should be accepted:
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vudot.u8 q0, q1, d16[0]
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vsdot.s8 q0, q1, d16[0]
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// CHECK-ERROR: error: operand must be a register in range [d0, d15]
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// CHECK-ERROR: vudot.u8 q0, q1, d16[0]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: operand must be a register in range [d0, d15]
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// CHECK-ERROR: vsdot.s8 q0, q1, d16[0]
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// CHECK-ERROR: ^
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