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20f66ad554
Select vector G_ADD for MIPS32 with MSA. We have to set bank for vector operands to fprb and selectImpl will do the rest. __builtin_msa_addv_<format> will be transformed into G_ADD in legalizeIntrinsic and selected in the same way. __builtin_msa_addvi_<format> will be directly selected into ADDVI_<format> in legalizeIntrinsic. MIR tests for it have unnecessary additional copies. Capture current state of tests with run-pass=legalizer with a test in test/CodeGen/MIR/Mips. Differential Revision: https://reviews.llvm.org/D68984 llvm-svn: 375501
28 lines
1.4 KiB
LLVM
28 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -stop-after=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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; Check there are no COPY instructions surrounding ADDVI_W instruction.
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; All virtual registers were created with createGenericVirtualRegister
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; which sets RegClassOrRegBank in VRegInfo.
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; Constraining register classes when G_INTRINSIC intrinsic(@llvm.mips.addvi.w)
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; gets selected into ADDVI_W works as expected.
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; Check that setRegClassOrRegBank.mir has same output.
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declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
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define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) {
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; P5600-LABEL: name: add_v4i32_builtin_imm
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; P5600: bb.1.entry:
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; P5600: liveins: $a0, $a1
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; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
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; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
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; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25
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; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
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; P5600: RetRA
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a, align 16
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%1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 25)
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store <4 x i32> %1, <4 x i32>* %c, align 16
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ret void
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}
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