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Amara Emerson 83ca134320 [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible.
In GlobalISel we may in some unfortunate circumstances generate PHIs with
operands that are on separate banks. If-conversion doesn't currently check for
that case and ends up generating a CSEL on AArch64 with incorrect register
operands.

Differential Revision: https://reviews.llvm.org/D72961
2020-01-21 16:51:31 -08:00
benchmarks
bindings Pass length of string in Go binding of CreateCompileUnit 2020-01-17 13:35:30 -08:00
cmake Remove AllTargetsAsmPrinters 2020-01-17 19:04:06 -05:00
docs Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
examples [ORC] Simplify use of lazyReexports with LLJIT. 2020-01-15 08:02:53 -08:00
include [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. 2020-01-21 16:51:31 -08:00
lib [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. 2020-01-21 16:51:31 -08:00
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runtimes [CMake] Prefer multi-target variables over generic target variables in runtimes build 2020-01-17 15:18:18 -08:00
test [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. 2020-01-21 16:51:31 -08:00
tools [llvm-exegesis] Fix support for LEA64_32r. 2020-01-21 13:58:23 +01:00
unittests [APInt] Fix tests that had wrong assumption about sdivs with negative quotient. 2020-01-21 13:53:01 -08:00
utils [gn build] Port fccd0da5ee6 2020-01-21 13:36:16 +00:00
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CMakeLists.txt Bump the trunk major version to 11 2020-01-15 13:38:01 +01:00
CODE_OWNERS.TXT [VE] Target stub for NEC SX-Aurora 2020-01-09 11:17:35 +01:00
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