Jakob Stoklund Olesen 83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. ... A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704		2010-05-26 17:27:12 +00:00
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Mangler.h	give Mangler access to TargetData.	2010-03-12 20:47:28 +00:00
SubtargetFeature.h	The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a	2010-05-11 00:30:02 +00:00
Target.td	Replace the SubRegSet tablegen class with a less error-prone mechanism.	2010-05-26 17:27:12 +00:00
TargetAsmBackend.h	MC: Eliminate MCAsmFixup, replace with MCFixup.	2010-05-26 15:18:56 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h	add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.	2010-03-24 23:07:47 +00:00
TargetInstrInfo.h	Implement @llvm.returnaddress. rdar://8015977.	2010-05-22 01:47:14 +00:00
TargetInstrItineraries.h	Initial support for different kinds of FU reservation.	2010-04-07 18:19:32 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h	Add a new section and accessor for TLS data.	2010-05-22 00:00:58 +00:00
TargetMachine.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetOpcodes.h	Add a pseudo instruction REG_SEQUENCE that takes a list of registers and	2010-05-01 00:28:44 +00:00
TargetOptions.h	Remove the -enable-sjlj-eh option, which doesn't do anything.	2010-05-02 15:36:26 +00:00
TargetRegisterInfo.h	Drop the SuperregHashTable. It is essentially the same as SubregHashTable.	2010-05-25 23:43:18 +00:00
TargetRegistry.h	Currently, createMachOStreamer() is invoked directly in llvm-mc which	2010-05-21 12:54:43 +00:00
TargetSchedule.td	Make processor FUs unique for given itinerary. This extends the limit of 32	2010-04-18 20:31:01 +00:00
TargetSelect.h
TargetSelectionDAG.td	finally remove the immAllOnesV_bc/immAllZerosV_bc patterns	2010-03-28 08:43:23 +00:00
TargetSelectionDAGInfo.h	Fix a comment.	2010-05-11 18:03:41 +00:00
TargetSubtarget.h