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c14a1eda84
The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
36 lines
910 B
LLVM
36 lines
910 B
LLVM
; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
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; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 1
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; 64-bit stores here do not use MMX.
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@M1 = external global <1 x i64>
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@M2 = external global <2 x i32>
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@S1 = external global <2 x i64>
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@S2 = external global <4 x i32>
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define void @test() {
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store <1 x i64> zeroinitializer, <1 x i64>* @M1
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store <2 x i32> zeroinitializer, <2 x i32>* @M2
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ret void
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}
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define void @test2() {
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store <1 x i64> < i64 -1 >, <1 x i64>* @M1
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store <2 x i32> < i32 -1, i32 -1 >, <2 x i32>* @M2
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ret void
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}
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define void @test3() {
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store <2 x i64> zeroinitializer, <2 x i64>* @S1
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store <4 x i32> zeroinitializer, <4 x i32>* @S2
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ret void
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}
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define void @test4() {
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store <2 x i64> < i64 -1, i64 -1>, <2 x i64>* @S1
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store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* @S2
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ret void
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}
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