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24c94cfae0
For eventually selecting llvm.nearbyint. Equivalent to the SelectionDAG nearbyint node. Update legalizer-info-validation.mir. Differential Revision: https://reviews.llvm.org/D60921 llvm-svn: 359201
561 lines
19 KiB
C++
561 lines
19 KiB
C++
//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target independent instruction opcodes.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
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///
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#ifndef HANDLE_TARGET_OPCODE
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#define HANDLE_TARGET_OPCODE(OPC, NUM)
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#endif
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/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
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///
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#ifndef HANDLE_TARGET_OPCODE_MARKER
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#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
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#endif
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/// Every instruction defined here must also appear in Target.td.
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///
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HANDLE_TARGET_OPCODE(PHI)
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HANDLE_TARGET_OPCODE(INLINEASM)
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HANDLE_TARGET_OPCODE(INLINEASM_BR)
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HANDLE_TARGET_OPCODE(CFI_INSTRUCTION)
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HANDLE_TARGET_OPCODE(EH_LABEL)
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HANDLE_TARGET_OPCODE(GC_LABEL)
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HANDLE_TARGET_OPCODE(ANNOTATION_LABEL)
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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HANDLE_TARGET_OPCODE(KILL)
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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HANDLE_TARGET_OPCODE(EXTRACT_SUBREG)
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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HANDLE_TARGET_OPCODE(INSERT_SUBREG)
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
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/// SUBREG_TO_REG - Assert the value of bits in a super register.
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/// The result of this instruction is the value of the second operand inserted
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/// into the subregister specified by the third operand. All other bits are
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/// assumed to be equal to the bits in the immediate integer constant in the
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/// first operand. This instruction just communicates information; No code
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/// should be generated.
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/// This is typically used after an instruction where the write to a subregister
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/// implicitly cleared the bits in the super registers.
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HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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HANDLE_TARGET_OPCODE(DBG_VALUE)
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/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic
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HANDLE_TARGET_OPCODE(DBG_LABEL)
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represents a consecutive sequence of sub-registers. It's used as a
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/// register coalescing / allocation aid and must be eliminated before code
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/// emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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HANDLE_TARGET_OPCODE(REG_SEQUENCE)
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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HANDLE_TARGET_OPCODE(COPY)
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/// BUNDLE - This instruction represents an instruction bundle. Instructions
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/// which immediately follow a BUNDLE instruction which are marked with
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/// 'InsideBundle' flag are inside the bundle.
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HANDLE_TARGET_OPCODE(BUNDLE)
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/// Lifetime markers.
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HANDLE_TARGET_OPCODE(LIFETIME_START)
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HANDLE_TARGET_OPCODE(LIFETIME_END)
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/// A Stackmap instruction captures the location of live variables at its
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/// position in the instruction stream. It is followed by a shadow of bytes
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/// that must lie within the function and not contain another stackmap.
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HANDLE_TARGET_OPCODE(STACKMAP)
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/// FEntry all - This is a marker instruction which gets translated into a raw fentry call.
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HANDLE_TARGET_OPCODE(FENTRY_CALL)
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/// Patchable call instruction - this instruction represents a call to a
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/// constant address, followed by a series of NOPs. It is intended to
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/// support optimizations for dynamic languages (such as javascript) that
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/// rewrite calls to runtimes with more efficient code sequences.
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/// This also implies a stack map.
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HANDLE_TARGET_OPCODE(PATCHPOINT)
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/// This pseudo-instruction loads the stack guard value. Targets which need
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/// to prevent the stack guard value or address from being spilled to the
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/// stack should override TargetLowering::emitLoadStackGuardNode and
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/// additionally expand this pseudo after register allocation.
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HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD)
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/// Call instruction with associated vm state for deoptimization and list
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/// of live pointers for relocation by the garbage collector. It is
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/// intended to support garbage collection with fully precise relocating
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/// collectors and deoptimizations in either the callee or caller.
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HANDLE_TARGET_OPCODE(STATEPOINT)
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/// Instruction that records the offset of a local stack allocation passed to
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/// llvm.localescape. It has two arguments: the symbol for the label and the
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/// frame index of the local stack allocation.
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HANDLE_TARGET_OPCODE(LOCAL_ESCAPE)
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/// Wraps a machine instruction which can fault, bundled with associated
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/// information on how to handle such a fault.
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/// For example loading instruction that may page fault, bundled with associated
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/// information on how to handle such a page fault. It is intended to support
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/// "zero cost" null checks in managed languages by allowing LLVM to fold
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/// comparisons into existing memory operations.
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HANDLE_TARGET_OPCODE(FAULTING_OP)
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/// Wraps a machine instruction to add patchability constraints. An
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/// instruction wrapped in PATCHABLE_OP has to either have a minimum
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/// size or be preceded with a nop of that size. The first operand is
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/// an immediate denoting the minimum size of the instruction, the
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/// second operand is an immediate denoting the opcode of the original
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/// instruction. The rest of the operands are the operands of the
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/// original instruction.
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HANDLE_TARGET_OPCODE(PATCHABLE_OP)
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/// This is a marker instruction which gets translated into a nop sled, useful
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/// for inserting instrumentation instructions at runtime.
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HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER)
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/// Wraps a return instruction and its operands to enable adding nop sleds
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/// either before or after the return. The nop sleds are useful for inserting
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/// instrumentation instructions at runtime.
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/// The patch here replaces the return instruction.
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HANDLE_TARGET_OPCODE(PATCHABLE_RET)
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/// This is a marker instruction which gets translated into a nop sled, useful
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/// for inserting instrumentation instructions at runtime.
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/// The patch here prepends the return instruction.
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/// The same thing as in x86_64 is not possible for ARM because it has multiple
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/// return instructions. Furthermore, CPU allows parametrized and even
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/// conditional return instructions. In the current ARM implementation we are
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/// making use of the fact that currently LLVM doesn't seem to generate
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/// conditional return instructions.
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/// On ARM, the same instruction can be used for popping multiple registers
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/// from the stack and returning (it just pops pc register too), and LLVM
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/// generates it sometimes. So we can't insert the sled between this stack
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/// adjustment and the return without splitting the original instruction into 2
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/// instructions. So on ARM, rather than jumping into the exit trampoline, we
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/// call it, it does the tracing, preserves the stack and returns.
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HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT)
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/// Wraps a tail call instruction and its operands to enable adding nop sleds
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/// either before or after the tail exit. We use this as a disambiguation from
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/// PATCHABLE_RET which specifically only works for return instructions.
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HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL)
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/// Wraps a logging call and its arguments with nop sleds. At runtime, this can
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/// be patched to insert instrumentation instructions.
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HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
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/// Wraps a typed logging call and its argument with nop sleds. At runtime, this
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/// can be patched to insert instrumentation instructions.
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HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL)
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HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
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/// The following generic opcodes are not supposed to appear after ISel.
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/// This is something we might want to relax, but for now, this is convenient
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/// to produce diagnostics.
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/// Generic ADD instruction. This is an integer add.
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HANDLE_TARGET_OPCODE(G_ADD)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
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/// Generic SUB instruction. This is an integer sub.
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HANDLE_TARGET_OPCODE(G_SUB)
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// Generic multiply instruction.
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HANDLE_TARGET_OPCODE(G_MUL)
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// Generic signed division instruction.
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HANDLE_TARGET_OPCODE(G_SDIV)
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// Generic unsigned division instruction.
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HANDLE_TARGET_OPCODE(G_UDIV)
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// Generic signed remainder instruction.
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HANDLE_TARGET_OPCODE(G_SREM)
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// Generic unsigned remainder instruction.
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HANDLE_TARGET_OPCODE(G_UREM)
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/// Generic bitwise and instruction.
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HANDLE_TARGET_OPCODE(G_AND)
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/// Generic bitwise or instruction.
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HANDLE_TARGET_OPCODE(G_OR)
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/// Generic bitwise exclusive-or instruction.
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HANDLE_TARGET_OPCODE(G_XOR)
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HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
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/// Generic PHI instruction with types.
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HANDLE_TARGET_OPCODE(G_PHI)
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/// Generic instruction to materialize the address of an alloca or other
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/// stack-based object.
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HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
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/// Generic reference to global value.
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HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE)
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/// Generic instruction to extract blocks of bits from the register given
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/// (typically a sub-register COPY after instruction selection).
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HANDLE_TARGET_OPCODE(G_EXTRACT)
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HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES)
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/// Generic instruction to insert blocks of bits from the registers given into
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/// the source.
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HANDLE_TARGET_OPCODE(G_INSERT)
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/// Generic instruction to paste a variable number of components together into a
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/// larger register.
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HANDLE_TARGET_OPCODE(G_MERGE_VALUES)
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/// Generic instruction to create a vector value from a number of scalar
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/// components.
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HANDLE_TARGET_OPCODE(G_BUILD_VECTOR)
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/// Generic instruction to create a vector value from a number of scalar
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/// components, which have types larger than the result vector elt type.
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HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC)
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/// Generic instruction to create a vector by concatenating multiple vectors.
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HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS)
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/// Generic pointer to int conversion.
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HANDLE_TARGET_OPCODE(G_PTRTOINT)
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/// Generic int to pointer conversion.
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HANDLE_TARGET_OPCODE(G_INTTOPTR)
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/// Generic bitcast. The source and destination types must be different, or a
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/// COPY is the relevant instruction.
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HANDLE_TARGET_OPCODE(G_BITCAST)
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/// INTRINSIC trunc intrinsic.
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HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
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/// INTRINSIC round intrinsic.
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HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
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/// Generic load (including anyext load)
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HANDLE_TARGET_OPCODE(G_LOAD)
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/// Generic signext load
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HANDLE_TARGET_OPCODE(G_SEXTLOAD)
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/// Generic zeroext load
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HANDLE_TARGET_OPCODE(G_ZEXTLOAD)
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/// Generic store.
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HANDLE_TARGET_OPCODE(G_STORE)
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/// Generic atomic cmpxchg with internal success check.
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HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS)
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/// Generic atomic cmpxchg.
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HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG)
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/// Generic atomicrmw.
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX)
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HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN)
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/// Generic conditional branch instruction.
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HANDLE_TARGET_OPCODE(G_BRCOND)
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/// Generic indirect branch instruction.
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HANDLE_TARGET_OPCODE(G_BRINDIRECT)
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/// Generic intrinsic use (without side effects).
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HANDLE_TARGET_OPCODE(G_INTRINSIC)
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/// Generic intrinsic use (with side effects).
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HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS)
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/// Generic extension allowing rubbish in high bits.
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HANDLE_TARGET_OPCODE(G_ANYEXT)
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/// Generic instruction to discard the high bits of a register. This differs
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/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate
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/// each element individually, G_EXTRACT will typically discard the high
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/// elements of the vector.
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HANDLE_TARGET_OPCODE(G_TRUNC)
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/// Generic integer constant.
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HANDLE_TARGET_OPCODE(G_CONSTANT)
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/// Generic floating constant.
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HANDLE_TARGET_OPCODE(G_FCONSTANT)
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/// Generic va_start instruction. Stores to its one pointer operand.
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HANDLE_TARGET_OPCODE(G_VASTART)
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/// Generic va_start instruction. Stores to its one pointer operand.
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HANDLE_TARGET_OPCODE(G_VAARG)
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// Generic sign extend
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HANDLE_TARGET_OPCODE(G_SEXT)
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// Generic zero extend
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HANDLE_TARGET_OPCODE(G_ZEXT)
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// Generic left-shift
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HANDLE_TARGET_OPCODE(G_SHL)
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// Generic logical right-shift
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HANDLE_TARGET_OPCODE(G_LSHR)
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// Generic arithmetic right-shift
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HANDLE_TARGET_OPCODE(G_ASHR)
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/// Generic integer-base comparison, also applicable to vectors of integers.
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HANDLE_TARGET_OPCODE(G_ICMP)
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/// Generic floating-point comparison, also applicable to vectors.
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HANDLE_TARGET_OPCODE(G_FCMP)
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/// Generic select.
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HANDLE_TARGET_OPCODE(G_SELECT)
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/// Generic unsigned add instruction, consuming the normal operands and
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/// producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_UADDO)
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/// Generic unsigned add instruction, consuming the normal operands plus a carry
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/// flag, and similarly producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_UADDE)
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/// Generic unsigned sub instruction, consuming the normal operands and
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/// producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_USUBO)
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/// Generic unsigned subtract instruction, consuming the normal operands plus a
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/// carry flag, and similarly producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_USUBE)
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/// Generic signed add instruction, producing the result and a signed overflow
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/// flag.
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HANDLE_TARGET_OPCODE(G_SADDO)
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/// Generic signed add instruction, consuming the normal operands plus a carry
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/// flag, and similarly producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_SADDE)
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/// Generic signed subtract instruction, producing the result and a signed
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/// overflow flag.
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HANDLE_TARGET_OPCODE(G_SSUBO)
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/// Generic signed sub instruction, consuming the normal operands plus a carry
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/// flag, and similarly producing the result and a carry flag.
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HANDLE_TARGET_OPCODE(G_SSUBE)
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/// Generic unsigned multiply instruction, producing the result and a signed
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/// overflow flag.
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HANDLE_TARGET_OPCODE(G_UMULO)
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/// Generic signed multiply instruction, producing the result and a signed
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/// overflow flag.
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HANDLE_TARGET_OPCODE(G_SMULO)
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// Multiply two numbers at twice the incoming bit width (unsigned) and return
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// the high half of the result.
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HANDLE_TARGET_OPCODE(G_UMULH)
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// Multiply two numbers at twice the incoming bit width (signed) and return
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// the high half of the result.
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HANDLE_TARGET_OPCODE(G_SMULH)
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/// Generic FP addition.
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HANDLE_TARGET_OPCODE(G_FADD)
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/// Generic FP subtraction.
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HANDLE_TARGET_OPCODE(G_FSUB)
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/// Generic FP multiplication.
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HANDLE_TARGET_OPCODE(G_FMUL)
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/// Generic FMA multiplication. Behaves like llvm fma intrinsic
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HANDLE_TARGET_OPCODE(G_FMA)
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/// Generic FP division.
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HANDLE_TARGET_OPCODE(G_FDIV)
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/// Generic FP remainder.
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HANDLE_TARGET_OPCODE(G_FREM)
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/// Generic FP exponentiation.
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HANDLE_TARGET_OPCODE(G_FPOW)
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/// Generic base-e exponential of a value.
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HANDLE_TARGET_OPCODE(G_FEXP)
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/// Generic base-2 exponential of a value.
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HANDLE_TARGET_OPCODE(G_FEXP2)
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/// Floating point base-e logarithm of a value.
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HANDLE_TARGET_OPCODE(G_FLOG)
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/// Floating point base-2 logarithm of a value.
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HANDLE_TARGET_OPCODE(G_FLOG2)
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/// Floating point base-10 logarithm of a value.
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HANDLE_TARGET_OPCODE(G_FLOG10)
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/// Generic FP negation.
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HANDLE_TARGET_OPCODE(G_FNEG)
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/// Generic FP extension.
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HANDLE_TARGET_OPCODE(G_FPEXT)
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/// Generic float to signed-int conversion
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HANDLE_TARGET_OPCODE(G_FPTRUNC)
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/// Generic float to signed-int conversion
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HANDLE_TARGET_OPCODE(G_FPTOSI)
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/// Generic float to unsigned-int conversion
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HANDLE_TARGET_OPCODE(G_FPTOUI)
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/// Generic signed-int to float conversion
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HANDLE_TARGET_OPCODE(G_SITOFP)
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/// Generic unsigned-int to float conversion
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HANDLE_TARGET_OPCODE(G_UITOFP)
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/// Generic FP absolute value.
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HANDLE_TARGET_OPCODE(G_FABS)
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/// Generic FP canonicalize value.
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HANDLE_TARGET_OPCODE(G_FCANONICALIZE)
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/// Generic pointer offset
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HANDLE_TARGET_OPCODE(G_GEP)
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/// Clear the specified number of low bits in a pointer. This rounds the value
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/// *down* to the given alignment.
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HANDLE_TARGET_OPCODE(G_PTR_MASK)
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/// Generic BRANCH instruction. This is an unconditional branch.
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HANDLE_TARGET_OPCODE(G_BR)
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/// Generic insertelement.
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HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
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/// Generic extractelement.
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HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
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/// Generic shufflevector.
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HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
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/// Generic count trailing zeroes.
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HANDLE_TARGET_OPCODE(G_CTTZ)
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/// Same as above, undefined for zero inputs.
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HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF)
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/// Generic count leading zeroes.
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HANDLE_TARGET_OPCODE(G_CTLZ)
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/// Same as above, undefined for zero inputs.
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HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF)
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/// Generic count bits.
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HANDLE_TARGET_OPCODE(G_CTPOP)
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/// Generic byte swap.
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HANDLE_TARGET_OPCODE(G_BSWAP)
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/// Floating point ceil.
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HANDLE_TARGET_OPCODE(G_FCEIL)
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/// Floating point cosine.
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HANDLE_TARGET_OPCODE(G_FCOS)
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/// Floating point sine.
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HANDLE_TARGET_OPCODE(G_FSIN)
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/// Floating point square root.
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HANDLE_TARGET_OPCODE(G_FSQRT)
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/// Floating point floor.
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HANDLE_TARGET_OPCODE(G_FFLOOR)
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/// Floating point round to next integer.
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HANDLE_TARGET_OPCODE(G_FRINT)
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/// Floating point round to nearest integer.
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HANDLE_TARGET_OPCODE(G_FNEARBYINT)
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/// Generic AddressSpaceCast.
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HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
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/// Generic block address
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HANDLE_TARGET_OPCODE(G_BLOCK_ADDR)
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// TODO: Add more generic opcodes as we move along.
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/// Marker for the end of the generic opcode.
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/// This is used to check if an opcode is in the range of the
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/// generic opcodes.
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BLOCK_ADDR)
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/// BUILTIN_OP_END - This must be the last enum value in this list.
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/// The target-specific post-isel opcode values start here.
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HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)
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